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aco: implement nir_op_bitz/bitnz
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23298>
This commit is contained in:
Georg Lehmann
Marge Bot
parent
6585209cdd
commit
573e98f34a
1 changed files with 132 additions and 1 deletions
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@ -1065,7 +1065,6 @@ emit_sopc_instruction(isel_context* ctx, nir_alu_instr* instr, aco_opcode op, Te
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assert(dst.regClass() == bld.lm);
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assert(dst.regClass() == bld.lm);
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assert(src0.type() == RegType::sgpr);
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assert(src0.type() == RegType::sgpr);
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assert(src1.type() == RegType::sgpr);
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assert(src1.type() == RegType::sgpr);
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assert(src0.regClass() == src1.regClass());
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/* Emit the SALU comparison instruction */
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/* Emit the SALU comparison instruction */
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Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
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Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
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@ -3916,6 +3915,138 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
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aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
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aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
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break;
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break;
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}
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}
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case nir_op_bitz:
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case nir_op_bitnz: {
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assert(instr->src[0].src.ssa->bit_size != 1);
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bool test0 = instr->op == nir_op_bitz;
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Temp src0 = get_alu_src(ctx, instr->src[0]);
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Temp src1 = get_alu_src(ctx, instr->src[1]);
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bool use_valu = src0.type() == RegType::vgpr || src1.type() == RegType::vgpr;
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if (!use_valu) {
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aco_opcode op = instr->src[0].src.ssa->bit_size == 64 ? aco_opcode::s_bitcmp1_b64
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: aco_opcode::s_bitcmp1_b32;
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if (test0)
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op = instr->src[0].src.ssa->bit_size == 64 ? aco_opcode::s_bitcmp0_b64
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: aco_opcode::s_bitcmp0_b32;
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emit_sopc_instruction(ctx, instr, op, dst);
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break;
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}
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/* We do not have a VALU version of s_bitcmp.
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* But if the second source is constant, we can use
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* v_cmp_class_f32's LUT to check the bit.
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* The LUT only has 10 entries, so extract a higher byte if we have to.
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* For sign bits comparision with 0 is better because v_cmp_class
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* can't be inverted.
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*/
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if (nir_src_is_const(instr->src[1].src)) {
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uint32_t bit = nir_alu_src_as_uint(instr->src[1]);
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bit &= instr->src[0].src.ssa->bit_size - 1;
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src0 = as_vgpr(ctx, src0);
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if (src0.regClass() == v2) {
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src0 = emit_extract_vector(ctx, src0, (bit & 32) != 0, v1);
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bit &= 31;
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}
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if (bit == 31) {
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bld.vopc(test0 ? aco_opcode::v_cmp_le_i32 : aco_opcode::v_cmp_gt_i32, Definition(dst),
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Operand::c32(0), src0);
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break;
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}
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if (bit == 15 && ctx->program->gfx_level >= GFX8) {
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bld.vopc(test0 ? aco_opcode::v_cmp_le_i16 : aco_opcode::v_cmp_gt_i16, Definition(dst),
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Operand::c32(0), src0);
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break;
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}
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/* For the bit==7 case, this is only faster than v_cmp_class if test0 && can_sdwa. */
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const bool can_sdwa = ctx->program->gfx_level >= GFX8 && ctx->program->gfx_level < GFX11;
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if ((bit & 0x7) == 7 && ((test0 && can_sdwa) || bit != 7)) {
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src0 = bld.pseudo(aco_opcode::p_extract, bld.def(v1), src0, Operand::c32(bit / 8),
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Operand::c32(8), Operand::c32(1));
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bld.vopc(test0 ? aco_opcode::v_cmp_le_i32 : aco_opcode::v_cmp_gt_i32, Definition(dst),
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Operand::c32(0), src0);
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break;
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}
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/* Avoid snan for bit 24. */
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if (bit == 24) {
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src0 = bld.pseudo(aco_opcode::p_extract, bld.def(v1), src0, Operand::c32(1),
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Operand::c32(16), Operand::c32(0));
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bit &= 0xf;
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}
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/* avoid +inf if we can use sdwa+qnan */
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if (bit > (can_sdwa ? 0x8 : 0x9)) {
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src0 = bld.pseudo(aco_opcode::p_extract, bld.def(v1), src0, Operand::c32(bit / 8),
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Operand::c32(8), Operand::c32(0));
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bit &= 0x7;
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}
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/* denorm and snan/qnan inputs are preserved using all float control modes. */
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static const std::pair<uint32_t, bool> float_lut[10] = {
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{0x7f800001, false}, /* snan */
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{-1, false}, /* qnan */
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{0xff800000, false}, /* -inf */
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{0xbf800000, false}, /* -normal (-1.0) */
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{1, true}, /* -denormal */
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{0, true}, /* -0.0 */
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{0, false}, /* +0.0 */
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{1, false}, /* +denormal */
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{0x3f800000, false}, /* +normal (+1.0) */
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{0x7f800000, false}, /* +inf */
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};
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Temp tmp = test0 ? bld.tmp(bld.lm) : dst;
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if (ctx->program->gfx_level >= GFX8 && bit == 0) {
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/* this can use s_movk. */
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bld.vopc(aco_opcode::v_cmp_class_f16, Definition(tmp),
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bld.copy(bld.def(s1), Operand::c32(0x7c01)), src0);
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} else {
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VALU_instruction& res =
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bld.vopc(aco_opcode::v_cmp_class_f32, Definition(tmp),
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bld.copy(bld.def(s1), Operand::c32(float_lut[bit].first)), src0)
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->valu();
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if (float_lut[bit].second) {
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res.format = asVOP3(res.format);
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res.neg[0] = true;
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}
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}
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if (test0)
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bld.sop1(Builder::s_not, Definition(dst), bld.def(s1, scc), tmp);
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break;
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}
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Temp res;
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aco_opcode op = test0 ? aco_opcode::v_cmp_eq_i32 : aco_opcode::v_cmp_lg_i32;
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if (instr->src[0].src.ssa->bit_size == 16) {
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op = test0 ? aco_opcode::v_cmp_eq_i16 : aco_opcode::v_cmp_lg_i16;
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if (ctx->program->gfx_level < GFX10)
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res = bld.vop2_e64(aco_opcode::v_lshlrev_b16, bld.def(v2b), src1, Operand::c32(1));
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else
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res = bld.vop3(aco_opcode::v_lshlrev_b16_e64, bld.def(v2b), src1, Operand::c32(1));
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res = bld.vop2(aco_opcode::v_and_b32, bld.def(v2b), src0, src1);
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} else if (instr->src[0].src.ssa->bit_size == 32) {
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res = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), src0, src1, Operand::c32(1));
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} else if (instr->src[0].src.ssa->bit_size == 64) {
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if (ctx->program->gfx_level < GFX8)
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res = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src0, src1);
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else
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res = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), src1, src0);
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res = emit_extract_vector(ctx, res, 0, v1);
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res = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand::c32(0x1), res);
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} else {
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isel_err(&instr->instr, "Unimplemented NIR instr bit size");
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}
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bld.vopc(op, Definition(dst), Operand::c32(0), res);
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break;
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}
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case nir_op_fddx:
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case nir_op_fddx:
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case nir_op_fddy:
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case nir_op_fddy:
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case nir_op_fddx_fine:
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case nir_op_fddx_fine:
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