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aco: implement vec2/3/4 with subdword operands

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Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
This commit is contained in:
Daniel Schürmann 2020-04-02 17:50:46 +01:00
parent 85521061d6
commit 5718347c2b
1 changed files with 30 additions and 6 deletions
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36
src/amd/compiler/aco_instruction_selection.cpp
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@ -941,14 +941,38 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
case nir_op_vec3:
case nir_op_vec4: {
std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
unsigned num = instr->dest.dest.ssa.num_components;
for (unsigned i = 0; i < num; ++i)
elems[i] = get_alu_src(ctx, instr->src[i]);
vec->operands[i] = Operand{elems[i]};
if (instr->dest.dest.ssa.bit_size >= 32 || dst.type() == RegType::vgpr) {
aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
for (unsigned i = 0; i < num; ++i)
vec->operands[i] = Operand{elems[i]};
vec->definitions[0] = Definition(dst);
ctx->block->instructions.emplace_back(std::move(vec));
ctx->allocated_vec.emplace(dst.id(), elems);
} else {
// TODO: that is a bit suboptimal..
Temp mask = bld.copy(bld.def(s1), Operand((1u << instr->dest.dest.ssa.bit_size) - 1));
for (unsigned i = 0; i < num - 1; ++i)
if (((i+1) * instr->dest.dest.ssa.bit_size) % 32)
elems[i] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), elems[i], mask);
for (unsigned i = 0; i < num; ++i) {
unsigned bit = i * instr->dest.dest.ssa.bit_size;
if (bit % 32 == 0) {
elems[bit / 32] = elems[i];
} else {
elems[i] = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc),
elems[i], Operand((i * instr->dest.dest.ssa.bit_size) % 32));
elems[bit / 32] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), elems[bit / 32], elems[i]);
}
}
if (dst.size() == 1)
bld.copy(Definition(dst), elems[0]);
else
bld.pseudo(aco_opcode::p_create_vector, Definition(dst), elems[0], elems[1]);
}
vec->definitions[0] = Definition(dst);
ctx->block->instructions.emplace_back(std::move(vec));
ctx->allocated_vec.emplace(dst.id(), elems);
break;
}
case nir_op_mov: {