diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c index ebb61d508a2..7d1c3ba1180 100644 --- a/src/gallium/drivers/iris/iris_resource.c +++ b/src/gallium/drivers/iris/iris_resource.c @@ -1498,50 +1498,6 @@ get_image_offset_el(const struct isl_surf *surf, unsigned level, unsigned z, } } -/** - * This function computes the tile_w (in bytes) and tile_h (in rows) of - * different tiling patterns. - */ -static void -iris_resource_get_tile_dims(enum isl_tiling tiling, uint32_t cpp, - uint32_t *tile_w, uint32_t *tile_h) -{ - switch (tiling) { - case ISL_TILING_X: - *tile_w = 512; - *tile_h = 8; - break; - case ISL_TILING_Y0: - *tile_w = 128; - *tile_h = 32; - break; - case ISL_TILING_LINEAR: - *tile_w = cpp; - *tile_h = 1; - break; - default: - unreachable("not reached"); - } - -} - -/** - * This function computes masks that may be used to select the bits of the X - * and Y coordinates that indicate the offset within a tile. If the BO is - * untiled, the masks are set to 0. - */ -static void -iris_resource_get_tile_masks(enum isl_tiling tiling, uint32_t cpp, - uint32_t *mask_x, uint32_t *mask_y) -{ - uint32_t tile_w_bytes, tile_h; - - iris_resource_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h); - - *mask_x = tile_w_bytes / cpp - 1; - *mask_y = tile_h - 1; -} - /** * Compute the offset (in bytes) from the start of the BO to the given x * and y coordinate. For tiled BOs, caller must ensure that x and y are @@ -1592,7 +1548,7 @@ iris_resource_get_tile_offsets(const struct iris_resource *res, const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format); const unsigned cpp = fmtl->bpb / 8; - iris_resource_get_tile_masks(res->surf.tiling, cpp, &mask_x, &mask_y); + isl_get_tile_masks(res->surf.tiling, cpp, &mask_x, &mask_y); get_image_offset_el(&res->surf, level, z, &x, &y); *tile_x = x & mask_x; diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 8de60d7584f..376703dcb75 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -2396,6 +2396,48 @@ isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2, enum isl_tiling tiling, isl_memcpy_type copy_type); +/** + * @brief computes the tile_w (in bytes) and tile_h (in rows) of + * different tiling patterns. + */ +static inline void +isl_get_tile_dims(enum isl_tiling tiling, uint32_t cpp, + uint32_t *tile_w, uint32_t *tile_h) +{ + switch (tiling) { + case ISL_TILING_X: + *tile_w = 512; + *tile_h = 8; + break; + case ISL_TILING_Y0: + *tile_w = 128; + *tile_h = 32; + break; + case ISL_TILING_LINEAR: + *tile_w = cpp; + *tile_h = 1; + break; + default: + unreachable("not reached"); + } +} + +/** + * @brief Computes masks that may be used to select the bits of the X + * and Y coordinates that indicate the offset within a tile. If the BO is + * untiled, the masks are set to 0. + */ +static inline void +isl_get_tile_masks(enum isl_tiling tiling, uint32_t cpp, + uint32_t *mask_x, uint32_t *mask_y) +{ + uint32_t tile_w_bytes, tile_h; + + isl_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h); + + *mask_x = tile_w_bytes / cpp - 1; + *mask_y = tile_h - 1; +} #ifdef __cplusplus } #endif diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 1291470d479..e139752e405 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -140,8 +140,8 @@ rebase_depth_stencil(struct brw_context *brw, struct intel_renderbuffer *irb, struct gl_context *ctx = &brw->ctx; uint32_t tile_mask_x = 0, tile_mask_y = 0; - intel_get_tile_masks(irb->mt->surf.tiling, irb->mt->cpp, - &tile_mask_x, &tile_mask_y); + isl_get_tile_masks(irb->mt->surf.tiling, irb->mt->cpp, + &tile_mask_x, &tile_mask_y); assert(!intel_miptree_level_has_hiz(irb->mt, irb->mt_level)); uint32_t tile_x = irb->draw_x & tile_mask_x; diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index d2892c48d3b..7f73f4be126 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -285,8 +285,8 @@ emit_copy_blit(struct brw_context *brw, src_buffer, src_pitch, src_offset, src_x, src_y, dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); - intel_get_tile_dims(src_tiling, cpp, &src_tile_w, &src_tile_h); - intel_get_tile_dims(dst_tiling, cpp, &dst_tile_w, &dst_tile_h); + isl_get_tile_dims(src_tiling, cpp, &src_tile_w, &src_tile_h); + isl_get_tile_dims(dst_tiling, cpp, &dst_tile_w, &dst_tile_h); /* For Tiled surfaces, the pitch has to be a multiple of the Tile width * (X direction width of the Tile). This is ensured while allocating the diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 0a65c9f9b14..680723c0741 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -1156,52 +1156,6 @@ intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt, *y = y_offset_sa; } - -/** - * This function computes the tile_w (in bytes) and tile_h (in rows) of - * different tiling patterns. If the BO is untiled, tile_w is set to cpp - * and tile_h is set to 1. - */ -void -intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp, - uint32_t *tile_w, uint32_t *tile_h) -{ - switch (tiling) { - case ISL_TILING_X: - *tile_w = 512; - *tile_h = 8; - break; - case ISL_TILING_Y0: - *tile_w = 128; - *tile_h = 32; - break; - case ISL_TILING_LINEAR: - *tile_w = cpp; - *tile_h = 1; - break; - default: - unreachable("not reached"); - } -} - - -/** - * This function computes masks that may be used to select the bits of the X - * and Y coordinates that indicate the offset within a tile. If the BO is - * untiled, the masks are set to 0. - */ -void -intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp, - uint32_t *mask_x, uint32_t *mask_y) -{ - uint32_t tile_w_bytes, tile_h; - - intel_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h); - - *mask_x = tile_w_bytes / cpp - 1; - *mask_y = tile_h - 1; -} - /** * Compute the offset (in bytes) from the start of the BO to the given x * and y coordinate. For tiled BOs, caller must ensure that x and y are @@ -1249,7 +1203,7 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, uint32_t x, y; uint32_t mask_x, mask_y; - intel_get_tile_masks(mt->surf.tiling, mt->cpp, &mask_x, &mask_y); + isl_get_tile_masks(mt->surf.tiling, mt->cpp, &mask_x, &mask_y); intel_miptree_get_image_offset(mt, level, slice, &x, &y); *tile_x = x & mask_x; diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index b8f53bde23e..fcf8e743855 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -463,14 +463,6 @@ void intel_get_image_dims(struct gl_texture_image *image, int *width, int *height, int *depth); -void -intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp, - uint32_t *mask_x, uint32_t *mask_y); - -void -intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp, - uint32_t *tile_w, uint32_t *tile_h); - uint32_t intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, GLuint level, GLuint slice,