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i965/fs: fix indirect load DF uniforms on BSW/BXT

Browse source 
The lowered BSW/BXT indirect move instructions had incorrect
source types, which luckily wasn't causing incorrect assembly to be
generated due to the bug fixed in the next patch, but would have
confused the remaining back-end IR infrastructure due to the mismatch
between the IR source types and the emitted machine code.

v2:
- Improve commit log (Curro)
- Fix read_size (Curro)
- Fix DF uniform array detection in assign_constant_locations() when
  it is acceded with 32-bit MOV_INDIRECTs in BSW/BXT.

v3:
- Move changes in assign_constant_locations() to other patch.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Samuel Iglesias Gonsálvez 2017-02-13 13:24:18 +01:00
parent a497ab6838
commit 56266df7ed
1 changed files with 20 additions and 21 deletions
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41
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
View file

@ -3815,31 +3815,30 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
unsigned read_size = instr->const_index[1] -
(instr->num_components - 1) * type_sz(dest.type);
fs_reg indirect_chv_high_32bit;
bool is_chv_bxt_64bit =
(devinfo->is_cherryview || devinfo->is_broxton) &&
type_sz(dest.type) == 8;
if (is_chv_bxt_64bit) {
indirect_chv_high_32bit = vgrf(glsl_type::uint_type);
/* Calculate indirect address to read high 32 bits */
bld.ADD(indirect_chv_high_32bit, indirect, brw_imm_ud(4));
}
bool supports_64bit_indirects =
!devinfo->is_cherryview && !devinfo->is_broxton;
for (unsigned j = 0; j < instr->num_components; j++) {
if (!is_chv_bxt_64bit) {
if (type_sz(dest.type) != 8 || supports_64bit_indirects) {
for (unsigned j = 0; j < instr->num_components; j++) {
bld.emit(SHADER_OPCODE_MOV_INDIRECT,
offset(dest, bld, j), offset(src, bld, j),
indirect, brw_imm_ud(read_size));
} else {
bld.emit(SHADER_OPCODE_MOV_INDIRECT,
subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, 0),
offset(src, bld, j),
indirect, brw_imm_ud(read_size));
bld.emit(SHADER_OPCODE_MOV_INDIRECT,
subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, 1),
offset(src, bld, j),
indirect_chv_high_32bit, brw_imm_ud(read_size));
}
} else {
const unsigned num_mov_indirects =
type_sz(dest.type) / type_sz(BRW_REGISTER_TYPE_UD);
/* We read a little bit less per MOV INDIRECT, as they are now
* 32-bits ones instead of 64-bit. Fix read_size then.
*/
const unsigned read_size_32bit = read_size -
(num_mov_indirects - 1) * type_sz(BRW_REGISTER_TYPE_UD);
for (unsigned j = 0; j < instr->num_components; j++) {
for (unsigned i = 0; i < num_mov_indirects; i++) {
bld.emit(SHADER_OPCODE_MOV_INDIRECT,
subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, i),
subscript(offset(src, bld, j), BRW_REGISTER_TYPE_UD, i),
indirect, brw_imm_ud(read_size_32bit));
}
}
}
}