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i965: Prefer Y-tiling on Gen6+.

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In the past, we preferred X-tiling for color buffers because our BLT
code couldn't handle Y-tiling.  However, the BLT paths have been largely
replaced by BLORP on Gen6+, which can handle any kind of tiling.

We hadn't measured any performance improvement in the past, but that's
probably because compressed textures were all untiled anyway.

Improves performance in GLB27_TRex_C24Z16_FixedTime by 7.69231%.

v2: Rebase on top of Eric's untiled-for-larger-than-aperture changes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke 2013-04-08 19:27:38 -07:00
parent 40e30c1ca1
commit 55ecc448b9
1 changed files with 1 additions and 1 deletions
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2
src/mesa/drivers/dri/intel/intel_mipmap_tree.c
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@ -346,7 +346,7 @@ intel_miptree_choose_tiling(struct intel_context *intel,
if (width0 >= 64) {
if (ALIGN(mt->total_width * mt->cpp, 512) < 32768)
return I915_TILING_X;
return intel->gen >= 6 ? I915_TILING_Y : I915_TILING_X;
perf_debug("%dx%d miptree too large to blit, falling back to untiled",
mt->total_width, mt->total_height);