diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index cae6e15eb73..40f99ee2408 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -339,6 +339,7 @@ public:
                             const fs_reg &urb_handle);
 
    void emit_barrier();
+   void emit_tcs_barrier();
 
    fs_reg get_timestamp(const brw::fs_builder &bld);
 
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 446f32e0ac3..13f04637a01 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2847,43 +2847,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
    case nir_intrinsic_control_barrier: {
       if (tcs_prog_data->instances == 1)
          break;
-
-      fs_reg m0 = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
-      fs_reg m0_2 = component(m0, 2);
-
-      const fs_builder chanbld = bld.exec_all().group(1, 0);
-
-      /* Zero the message header */
-      bld.exec_all().MOV(m0, brw_imm_ud(0u));
-
-      if (devinfo->verx10 >= 125) {
-         /* From BSpec: 54006, mov r0.2[31:24] into m0.2[31:24] and m0.2[23:16] */
-         fs_reg m0_10ub = component(retype(m0, BRW_REGISTER_TYPE_UB), 10);
-         fs_reg r0_11ub =
-            stride(suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UB), 11),
-                   0, 1, 0);
-         bld.exec_all().group(2, 0).MOV(m0_10ub, r0_11ub);
-      } else if (devinfo->ver >= 11) {
-         chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
-                     brw_imm_ud(INTEL_MASK(30, 24)));
-
-         /* Set the Barrier Count and the enable bit */
-         chanbld.OR(m0_2, m0_2,
-                    brw_imm_ud(tcs_prog_data->instances << 8 | (1 << 15)));
-      } else {
-         /* Copy "Barrier ID" from r0.2, bits 16:13 */
-         chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
-                     brw_imm_ud(INTEL_MASK(16, 13)));
-
-         /* Shift it up to bits 27:24. */
-         chanbld.SHL(m0_2, m0_2, brw_imm_ud(11));
-
-         /* Set the Barrier Count and the enable bit */
-         chanbld.OR(m0_2, m0_2,
-                    brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15)));
-      }
-
-      bld.emit(SHADER_OPCODE_BARRIER, bld.null_reg_ud(), m0);
+      emit_tcs_barrier();
       break;
    }
 
diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp
index 91be715653b..f63a34dc9c1 100644
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/intel/compiler/brw_fs_visitor.cpp
@@ -1130,6 +1130,50 @@ fs_visitor::emit_barrier()
    bld.exec_all().emit(SHADER_OPCODE_BARRIER, reg_undef, payload);
 }
 
+void
+fs_visitor::emit_tcs_barrier()
+{
+   assert(stage == MESA_SHADER_TESS_CTRL);
+   struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
+
+   fs_reg m0 = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
+   fs_reg m0_2 = component(m0, 2);
+
+   const fs_builder chanbld = bld.exec_all().group(1, 0);
+
+   /* Zero the message header */
+   bld.exec_all().MOV(m0, brw_imm_ud(0u));
+
+   if (devinfo->verx10 >= 125) {
+      /* From BSpec: 54006, mov r0.2[31:24] into m0.2[31:24] and m0.2[23:16] */
+      fs_reg m0_10ub = component(retype(m0, BRW_REGISTER_TYPE_UB), 10);
+      fs_reg r0_11ub =
+         stride(suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UB), 11),
+                0, 1, 0);
+      bld.exec_all().group(2, 0).MOV(m0_10ub, r0_11ub);
+   } else if (devinfo->ver >= 11) {
+      chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
+                  brw_imm_ud(INTEL_MASK(30, 24)));
+
+      /* Set the Barrier Count and the enable bit */
+      chanbld.OR(m0_2, m0_2,
+                 brw_imm_ud(tcs_prog_data->instances << 8 | (1 << 15)));
+   } else {
+      /* Copy "Barrier ID" from r0.2, bits 16:13 */
+      chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
+                  brw_imm_ud(INTEL_MASK(16, 13)));
+
+      /* Shift it up to bits 27:24. */
+      chanbld.SHL(m0_2, m0_2, brw_imm_ud(11));
+
+      /* Set the Barrier Count and the enable bit */
+      chanbld.OR(m0_2, m0_2,
+                 brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15)));
+   }
+
+   bld.emit(SHADER_OPCODE_BARRIER, bld.null_reg_ud(), m0);
+}
+
 fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
                        void *mem_ctx,
                        const brw_base_prog_key *key,