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nvk: Support extended dynamic state for tessellation domain origin
The tessellation domain origin, type, prims and spacing are all pushed together in SET_TESSELLATION_PARAMETERS. So to support domain origin as dynamic we need to push all these together when the state is dynamically changed or when a new tessellation shader is bound. This is also needed for EXT_shader_object. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24872>
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parent
1319cfb40d
commit
55c8f5e288
4 changed files with 44 additions and 32 deletions
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@ -930,6 +930,15 @@ nvk_cmd_bind_graphics_pipeline(struct nvk_cmd_buffer *cmd,
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cmd->state.gfx.pipeline = pipeline;
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vk_cmd_set_dynamic_graphics_state(&cmd->vk, &pipeline->dynamic);
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/* When a pipeline with tess shaders is bound we need to re-upload the
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* tessellation parameters at flush_ts_state, as the domain origin can be
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* dynamic.
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*/
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if (nvk_shader_is_enabled(&pipeline->base.shaders[MESA_SHADER_TESS_EVAL])) {
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BITSET_SET(cmd->vk.dynamic_graphics_state.dirty,
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MESA_VK_DYNAMIC_TS_DOMAIN_ORIGIN);
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}
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struct nv_push *p = nvk_cmd_buffer_push(cmd, pipeline->push_dw_count);
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nv_push_raw(p, pipeline->push_data, pipeline->push_dw_count);
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}
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@ -999,11 +1008,34 @@ nvk_flush_ts_state(struct nvk_cmd_buffer *cmd)
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{
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const struct vk_dynamic_graphics_state *dyn =
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&cmd->vk.dynamic_graphics_state;
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struct nv_push *p = nvk_cmd_buffer_push(cmd, 4);
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if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_TS_PATCH_CONTROL_POINTS)) {
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struct nv_push *p = nvk_cmd_buffer_push(cmd, 2);
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P_IMMD(p, NV9097, SET_PATCH, dyn->ts.patch_control_points);
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}
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if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_TS_DOMAIN_ORIGIN)) {
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const struct nvk_graphics_pipeline *pipeline= cmd->state.gfx.pipeline;
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const struct nvk_shader *shader =
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&pipeline->base.shaders[MESA_SHADER_TESS_EVAL];
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if (nvk_shader_is_enabled(shader)) {
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enum nak_ts_prims prims = shader->info.ts.prims;
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/* When the origin is lower-left, we have to flip the winding order */
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if (dyn->ts.domain_origin == VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT) {
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if (prims == NAK_TS_PRIMS_TRIANGLES_CW)
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prims = NAK_TS_PRIMS_TRIANGLES_CCW;
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else if (prims == NAK_TS_PRIMS_TRIANGLES_CCW)
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prims = NAK_TS_PRIMS_TRIANGLES_CW;
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}
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P_MTHD(p, NV9097, SET_TESSELLATION_PARAMETERS);
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P_NV9097_SET_TESSELLATION_PARAMETERS(p, {
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shader->info.ts.domain,
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shader->info.ts.spacing,
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prims
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});
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}
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}
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}
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static void
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@ -113,27 +113,6 @@ static const uint32_t mesa_to_nv9097_shader_type[] = {
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[MESA_SHADER_FRAGMENT] = NV9097_SET_PIPELINE_SHADER_TYPE_PIXEL,
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};
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static void
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emit_tessellation_paramaters(struct nv_push *p,
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const struct nvk_shader *shader,
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const struct vk_tessellation_state *state)
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{
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enum nak_ts_prims prims = shader->info.ts.prims;
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/* When the origin is lower-left, we have to flip the winding order */
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if (state->domain_origin == VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT) {
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if (prims == NAK_TS_PRIMS_TRIANGLES_CW)
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prims = NAK_TS_PRIMS_TRIANGLES_CCW;
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else if (prims == NAK_TS_PRIMS_TRIANGLES_CCW)
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prims = NAK_TS_PRIMS_TRIANGLES_CW;
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}
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P_MTHD(p, NV9097, SET_TESSELLATION_PARAMETERS);
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P_NV9097_SET_TESSELLATION_PARAMETERS(p, {
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shader->info.ts.domain,
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shader->info.ts.spacing,
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prims
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});
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}
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static void
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merge_tess_info(struct shader_info *tes_info, struct shader_info *tcs_info)
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{
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@ -267,11 +246,11 @@ nvk_graphics_pipeline_create(struct nvk_device *dev,
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uint32_t idx = mesa_to_nv9097_shader_type[stage];
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P_IMMD(p, NV9097, SET_PIPELINE_SHADER(idx), {
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.enable = shader->upload_size > 0,
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.enable = nvk_shader_is_enabled(shader),
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.type = mesa_to_nv9097_shader_type[stage],
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});
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if (shader->upload_size == 0)
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if (!nvk_shader_is_enabled(shader))
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continue;
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if (stage != MESA_SHADER_FRAGMENT)
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@ -294,6 +273,8 @@ nvk_graphics_pipeline_create(struct nvk_device *dev,
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switch (stage) {
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case MESA_SHADER_VERTEX:
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case MESA_SHADER_GEOMETRY:
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case MESA_SHADER_TESS_CTRL:
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case MESA_SHADER_TESS_EVAL:
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break;
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case MESA_SHADER_FRAGMENT:
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@ -329,13 +310,6 @@ nvk_graphics_pipeline_create(struct nvk_device *dev,
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shader->info.fs.uses_sample_shading;
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break;
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case MESA_SHADER_TESS_CTRL:
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break;
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case MESA_SHADER_TESS_EVAL:
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emit_tessellation_paramaters(p, shader, state.ts);
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break;
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default:
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unreachable("Unsupported shader stage");
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}
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@ -389,7 +389,7 @@ nvk_get_device_features(const struct nv_device_info *info,
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.extendedDynamicState2PatchControlPoints = true,
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/* VK_EXT_extended_dynamic_state3 */
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.extendedDynamicState3TessellationDomainOrigin = false,
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.extendedDynamicState3TessellationDomainOrigin = true,
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.extendedDynamicState3DepthClampEnable = true,
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.extendedDynamicState3PolygonMode = true,
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.extendedDynamicState3RasterizationSamples = false,
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@ -64,6 +64,12 @@ nvk_shader_address(const struct nvk_shader *shader)
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return shader->upload_addr + shader->upload_padding;
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}
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static inline bool
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nvk_shader_is_enabled(const struct nvk_shader *shader)
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{
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return shader->upload_size > 0;
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}
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VkShaderStageFlags nvk_nak_stages(const struct nv_device_info *info);
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uint64_t
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