From 55aeac7af46f5a4d9b40f2fa7fb2d6ca285f9202 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Thu, 7 Jan 2021 13:29:35 +0000 Subject: [PATCH] ac/nir: implement nir_op_vec5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since sparse fetch/load uses vec5 destinations, it may be possible that we encounter nir_op_vec5. Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Part-of: --- src/amd/llvm/ac_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 19de5c4ece4..0555fe695ba 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -561,6 +561,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) case nir_op_vec2: case nir_op_vec3: case nir_op_vec4: + case nir_op_vec5: case nir_op_unpack_32_2x16: case nir_op_unpack_64_2x32: case nir_op_unpack_64_4x16: @@ -900,6 +901,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) case nir_op_vec2: case nir_op_vec3: case nir_op_vec4: + case nir_op_vec5: for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) src[i] = ac_to_integer(&ctx->ac, src[i]); result = ac_build_gather_values(&ctx->ac, src, num_components);