From 5588cfe5d10db5468c1afd3a3ec5edfcda8ff84c Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Wed, 27 May 2026 09:12:32 -0700 Subject: [PATCH] brw: Use nir_opt_shrink_stores MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We never called this for scalar shader stages, and nobody is quite sure why. Some speculation is that there was no benefit before load / store merging was added. There was also some speculation that it was harmful before load / store merging could handle holes. Given that only ~20 shaders in shader-db were affected, it's also possible that no shaders were affected in scalar in scalar stages at the time it was first added. We may never know. ¯\_(ツ)_/¯ Calling it inside the loop had no impact, so call it once after the loop. I don't know why this hurts Ice Lake but helps every other platform. shader-db: All Iris platforms had similar results. (Lunar Lake shown) total instructions in shared programs: 17089936 -> 17089861 (<.01%) instructions in affected programs: 23685 -> 23610 (-0.32%) helped: 19 / HURT: 0 total cycles in shared programs: 864096306 -> 864099466 (<.01%) cycles in affected programs: 1981658 -> 1984818 (0.16%) helped: 12 / HURT: 7 LOST: 0 GAINED: 2 fossil-db: Lunar Lake Totals: Instrs: 914554524 -> 914548221 (-0.00%); split: -0.00%, +0.00% CodeSize: 12887150560 -> 12887094496 (-0.00%); split: -0.00%, +0.00% Cycle count: 100103979198 -> 100103691332 (-0.00%); split: -0.00%, +0.00% Spill count: 3459811 -> 3459692 (-0.00%) Fill count: 4909786 -> 4909516 (-0.01%) Max live registers: 191838197 -> 191831367 (-0.00%); split: -0.00%, +0.00% Max dispatch width: 48514528 -> 48514576 (+0.00%) Non SSA regs after NIR: 136347693 -> 136146918 (-0.15%); split: -0.15%, +0.00% Totals from 17915 (0.89% of 2003490) affected shaders: Instrs: 4205005 -> 4198702 (-0.15%); split: -0.15%, +0.00% CodeSize: 57002192 -> 56946128 (-0.10%); split: -0.14%, +0.05% Cycle count: 253980589 -> 253692723 (-0.11%); split: -0.26%, +0.14% Spill count: 2026 -> 1907 (-5.87%) Fill count: 2636 -> 2366 (-10.24%) Max live registers: 1174571 -> 1167741 (-0.58%); split: -0.59%, +0.01% Max dispatch width: 430368 -> 430416 (+0.01%) Non SSA regs after NIR: 1005266 -> 804491 (-19.97%); split: -19.97%, +0.00% Meteor Lake, DG2, Tiger Lake, Ice Lake, and Skylake had similar results. (Meteor Lake shown) Totals: Instrs: 989799269 -> 989778469 (-0.00%); split: -0.00%, +0.00% CodeSize: 16516706896 -> 16516376256 (-0.00%); split: -0.00%, +0.00% Subgroup size: 27542464 -> 27542528 (+0.00%) Send messages: 44446154 -> 44446153 (-0.00%) Cycle count: 91362833728 -> 91362723256 (-0.00%); split: -0.00%, +0.00% Spill count: 3713932 -> 3713758 (-0.00%) Fill count: 5001432 -> 5001144 (-0.01%) Max live registers: 121358101 -> 121356271 (-0.00%); split: -0.00%, +0.00% Max dispatch width: 38061600 -> 38060544 (-0.00%); split: +0.00%, -0.00% Non SSA regs after NIR: 161013837 -> 160662598 (-0.22%); split: -0.22%, +0.00% Totals from 22841 (1.00% of 2278082) affected shaders: Instrs: 4974061 -> 4953261 (-0.42%); split: -0.42%, +0.00% CodeSize: 77949200 -> 77618560 (-0.42%); split: -0.44%, +0.02% Subgroup size: 64 -> 128 (+100.00%) Send messages: 279204 -> 279203 (-0.00%) Cycle count: 176737437 -> 176626965 (-0.06%); split: -0.29%, +0.23% Spill count: 2362 -> 2188 (-7.37%) Fill count: 3162 -> 2874 (-9.11%) Max live registers: 906456 -> 904626 (-0.20%); split: -0.21%, +0.01% Max dispatch width: 451784 -> 450728 (-0.23%); split: +0.01%, -0.24% Non SSA regs after NIR: 1477247 -> 1126008 (-23.78%); split: -23.78%, +0.00% Acked-by: Alyssa Rosenzweig Part-of: --- src/intel/compiler/brw/brw_nir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw/brw_nir.c b/src/intel/compiler/brw/brw_nir.c index 2d72d8c2931..0dc19d017f4 100644 --- a/src/intel/compiler/brw/brw_nir.c +++ b/src/intel/compiler/brw/brw_nir.c @@ -1992,6 +1992,7 @@ brw_nir_optimize(brw_pass_tracker *pt) LOOP_OPT(nir_lower_pack); } while (pt->progress); + OPT(nir_opt_shrink_stores, true); OPT(nir_remove_dead_variables, nir_var_function_temp, NULL); }