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r600g: handle the write all cbufs property.

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This only works on r600/r700 so far, evergreen doesn't appear
to have the multiwrite enable bit in the color control, so we
may have to actually do a shader rewrite on EG hardware.

remove some duplicate code reg defines also.

Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2011-01-31 10:01:06 +10:00
parent f668b464c0
commit 5555cd776b
5 changed files with 16 additions and 30 deletions
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2
src/gallium/drivers/r600/evergreen_state.c
View file

@ -103,7 +103,7 @@ static void *evergreen_create_blend_state(struct pipe_context *ctx,
}
blend->cb_target_mask = target_mask;
r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
color_control, 0xFFFFFFFF, NULL);
color_control, 0xFFFFFFFD, NULL);
r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
for (int i = 0; i < 8; i++) {

3
src/gallium/drivers/r600/evergreend.h
View file

@ -430,9 +430,6 @@
#define S_028808_FOG_ENABLE(x) (((x) & 0x1) << 0)
#define G_028808_FOG_ENABLE(x) (((x) >> 0) & 0x1)
#define C_028808_FOG_ENABLE 0xFFFFFFFE
#define S_028808_MULTIWRITE_ENABLE(x) (((x) & 0x1) << 1)
#define G_028808_MULTIWRITE_ENABLE(x) (((x) >> 1) & 0x1)
#define C_028808_MULTIWRITE_ENABLE 0xFFFFFFFD
#define S_028808_DITHER_ENABLE(x) (((x) & 0x1) << 2)
#define G_028808_DITHER_ENABLE(x) (((x) >> 2) & 0x1)
#define C_028808_DITHER_ENABLE 0xFFFFFFFB

15
src/gallium/drivers/r600/r600_shader.c
View file

@ -175,6 +175,13 @@ static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shade
R_0288CC_SQ_PGM_CF_OFFSET_PS,
0x00000000, 0xFFFFFFFF, NULL);
if (rshader->fs_write_all) {
r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
S_028808_MULTIWRITE_ENABLE(1),
S_028808_MULTIWRITE_ENABLE(1),
NULL);
}
if (rshader->uses_kill) {
/* only set some bits here, the other bits are set in the dsa state */
r600_pipe_state_add_reg(rstate,
@ -495,6 +502,7 @@ static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader, u32 **literals)
{
struct tgsi_full_immediate *immediate;
struct tgsi_full_property *property;
struct r600_shader_ctx ctx;
struct r600_bc_output output[32];
unsigned output_done, noutput;
@ -563,7 +571,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
ctx.nliterals = 0;
ctx.literals = NULL;
shader->fs_write_all = FALSE;
while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
tgsi_parse_token(&ctx.parse);
switch (ctx.parse.FullToken.Token.Type) {
@ -602,6 +610,11 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
goto out_err;
break;
case TGSI_TOKEN_TYPE_PROPERTY:
property = &ctx.parse.FullToken.FullProperty;
if (property->Property.PropertyName == TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS) {
if (property->u[0].Data == 1)
shader->fs_write_all = TRUE;
}
break;
default:
R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);

1
src/gallium/drivers/r600/r600_shader.h
View file

@ -45,6 +45,7 @@ struct r600_shader {
struct r600_shader_io output[32];
enum radeon_family family;
boolean uses_kill;
boolean fs_write_all;
};
int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader, u32 **literals);

25
src/gallium/drivers/r600/r600d.h
View file

@ -2332,31 +2332,6 @@
#define R_0280D4_CB_COLOR5_TILE 0x0280D4
#define R_0280D8_CB_COLOR6_TILE 0x0280D8
#define R_0280DC_CB_COLOR7_TILE 0x0280DC
#define R_028808_CB_COLOR_CONTROL 0x028808
#define S_028808_FOG_ENABLE(x) (((x) & 0x1) << 0)
#define G_028808_FOG_ENABLE(x) (((x) >> 0) & 0x1)
#define C_028808_FOG_ENABLE 0xFFFFFFFE
#define S_028808_MULTIWRITE_ENABLE(x) (((x) & 0x1) << 1)
#define G_028808_MULTIWRITE_ENABLE(x) (((x) >> 1) & 0x1)
#define C_028808_MULTIWRITE_ENABLE 0xFFFFFFFD
#define S_028808_DITHER_ENABLE(x) (((x) & 0x1) << 2)
#define G_028808_DITHER_ENABLE(x) (((x) >> 2) & 0x1)
#define C_028808_DITHER_ENABLE 0xFFFFFFFB
#define S_028808_DEGAMMA_ENABLE(x) (((x) & 0x1) << 3)
#define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1)
#define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7
#define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4)
#define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7)
#define C_028808_SPECIAL_OP 0xFFFFFF8F
#define S_028808_PER_MRT_BLEND(x) (((x) & 0x1) << 7)
#define G_028808_PER_MRT_BLEND(x) (((x) >> 7) & 0x1)
#define C_028808_PER_MRT_BLEND 0xFFFFFF7F
#define S_028808_TARGET_BLEND_ENABLE(x) (((x) & 0xFF) << 8)
#define G_028808_TARGET_BLEND_ENABLE(x) (((x) >> 8) & 0xFF)
#define C_028808_TARGET_BLEND_ENABLE 0xFFFF00FF
#define S_028808_ROP3(x) (((x) & 0xFF) << 16)
#define G_028808_ROP3(x) (((x) >> 16) & 0xFF)
#define C_028808_ROP3 0xFF00FFFF
#define R_028614_SPI_VS_OUT_ID_0 0x028614
#define S_028614_SEMANTIC_0(x) (((x) & 0xFF) << 0)
#define G_028614_SEMANTIC_0(x) (((x) >> 0) & 0xFF)