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radeon/llvm: Use -1 as true value for SET* integer instructions

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This commit is contained in:
Tom Stellard 2012-05-23 12:25:04 -04:00
parent 86dfae1103
commit 5523502ff9
3 changed files with 28 additions and 32 deletions
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36
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
View file

@ -119,10 +119,6 @@ SDValue AMDGPUTargetLowering::LowerSELECT_CC(SDValue Op,
ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
SDValue Temp;
//cmovlog = src0 != 0.0f ? src1 : src2
//cmovlog = src0 == 0.0f ? src2 : src1
//cnde = src0 == 0.0f ? src1 : src2
// LHS and RHS are guaranteed to be the same value type
EVT CompareVT = LHS.getValueType();
@ -151,16 +147,16 @@ SDValue AMDGPUTargetLowering::LowerSELECT_CC(SDValue Op,
RHS = DAG.getNode(ConversionOp, DL, VT, RHS);
}
// If true is 1 and false is 0 or vice-versa we can handle this with a native
// instruction (SET* instructions).
if ((isOne(True) && isZero(False))) {
// If True is a hardware TRUE value and False is a hardware FALSE value or
// vice-versa we can handle this with a native instruction (SET* instructions).
if ((isHWTrueValue(True) && isHWFalseValue(False))) {
return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
}
// XXX If true is 0 and 1 is false, we can handle this with a native
// instruction, but we need to swap true and false and change the
// conditional.
if (isOne(False) && isZero(True)) {
// XXX If True is a hardware TRUE value and False is a hardware FALSE value,
// we can handle this with a native instruction, but we need to swap true
// and false and change the conditional.
if (isHWTrueValue(False) && isHWFalseValue(True)) {
}
// XXX Check if we can lower this to a SELECT or if it is supported by a native
@ -196,14 +192,14 @@ SDValue AMDGPUTargetLowering::LowerSELECT_CC(SDValue Op,
// If we make it this for it means we have no native instructions to handle
// this SELECT_CC, so we must lower it.
SDValue One, Zero;
SDValue HWTrue, HWFalse;
if (VT == MVT::f32) {
One = DAG.getConstantFP(1.0f, VT);
Zero = DAG.getConstantFP(0.0f, VT);
HWTrue = DAG.getConstantFP(1.0f, VT);
HWFalse = DAG.getConstantFP(0.0f, VT);
} else if (VT == MVT::i32) {
One = DAG.getConstant(1, VT);
Zero = DAG.getConstant(0, VT);
HWTrue = DAG.getConstant(-1, VT);
HWFalse = DAG.getConstant(0, VT);
}
else {
assert(!"Unhandled value type in LowerSELECT_CC");
@ -211,7 +207,7 @@ SDValue AMDGPUTargetLowering::LowerSELECT_CC(SDValue Op,
// Lower this unsupported SELECT_CC into a combination of two supported
// SELECT_CC operations.
SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, One, Zero, CC);
SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, HWTrue, HWFalse, CC);
return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
}
@ -220,18 +216,18 @@ SDValue AMDGPUTargetLowering::LowerSELECT_CC(SDValue Op,
// Helper functions
//===----------------------------------------------------------------------===//
bool AMDGPUTargetLowering::isOne(SDValue Op) const
bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const
{
if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
return CFP->isExactlyValue(1.0);
}
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
return C->isOne();
return C->isAllOnesValue();
}
return false;
}
bool AMDGPUTargetLowering::isZero(SDValue Op) const
bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const
{
if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
return CFP->getValueAPF().isZero();

4
src/gallium/drivers/radeon/AMDGPUISelLowering.h
View file

@ -37,8 +37,8 @@ protected:
MachineRegisterInfo & MRI, const TargetInstrInfo * TII,
unsigned reg) const;
bool isOne(SDValue Op) const;
bool isZero(SDValue Op) const;
bool isHWTrueValue(SDValue Op) const;
bool isHWFalseValue(SDValue Op) const;
public:
AMDGPUTargetLowering(TargetMachine &TM);

20
src/gallium/drivers/radeon/R600Instructions.td
View file

@ -446,7 +446,7 @@ def MIN_UINT : R600_2OP <
def SETE_INT : R600_2OP <
0x3A, "SETE_INT",
[(set (i32 R600_Reg32:$dst),
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, 1, 0, SETEQ))]
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
>;
// let AMDILOp = AMDILInst.IEQ;
@ -454,13 +454,13 @@ def SETE_INT : R600_2OP <
def SETGT_INT : R600_2OP <
0x3B, "SGT_INT",
[(set (i32 R600_Reg32:$dst),
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, 1, 0, SETGT))]
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
>;
def SETGE_INT : R600_2OP <
0x3C, "SETGE_INT",
[(set (i32 R600_Reg32:$dst),
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, 1, 0, SETGE))]
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
>;
// let AMDILOp = AMDILInst.IGE;
@ -468,7 +468,7 @@ def SETGE_INT : R600_2OP <
def SETNE_INT : R600_2OP <
0x3D, "SETNE_INT",
[(set (i32 R600_Reg32:$dst),
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, 1, 0, SETNE))]
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
>;
//let AMDILOp = AMDILInst.INE;
@ -476,7 +476,7 @@ def SETNE_INT : R600_2OP <
def SETGT_UINT : R600_2OP <
0x3E, "SETGT_UINT",
[(set (i32 R600_Reg32:$dst),
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, 1, 0, SETUGT))]
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
>;
// let AMDILOp = AMDILInst.UGT;
@ -484,7 +484,7 @@ def SETGT_UINT : R600_2OP <
def SETGE_UINT : R600_2OP <
0x3F, "SETGE_UINT",
[(set (i32 R600_Reg32:$dst),
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, 1, 0, SETUGE))]
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
>;
// let AMDILOp = AMDILInst.UGE;
@ -1134,25 +1134,25 @@ def : Pat <
// SETGT_INT reverse args
def : Pat <
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, 1, 0, SETLT),
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
(SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
>;
// SETGE_INT reverse args
def : Pat <
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, 1, 0, SETLE),
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
(SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
>;
// SETGT_UINT reverse args
def : Pat <
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, 1, 0, SETULT),
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
(SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
>;
// SETGE_UINT reverse args
def : Pat <
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, 1, 0, SETULE),
(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
(SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1)
>;