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i965/miptree: Delete MIPTREE_LAYOUT_TILING_(Y|ANY)
The only force tiling flag we really care about is LAYOUT_TILING_NONE. The others don't actually do anything but add confusion. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
parent
1779499166
commit
55116839d9
6 changed files with 8 additions and 24 deletions
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@ -944,8 +944,7 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
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struct intel_mipmap_tree *new_mt;
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int width, height, depth;
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uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
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MIPTREE_LAYOUT_TILING_ANY;
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uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
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intel_get_image_dims(rb->TexImage, &width, &height, &depth);
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@ -628,16 +628,6 @@ make_separate_stencil_surface(struct brw_context *brw,
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return true;
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}
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static bool
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force_linear_tiling(uint32_t layout_flags)
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{
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/* ANY includes NONE and Y bit. */
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if (layout_flags & MIPTREE_LAYOUT_TILING_Y)
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return false;
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return layout_flags & MIPTREE_LAYOUT_TILING_NONE;
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}
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static struct intel_mipmap_tree *
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miptree_create(struct brw_context *brw,
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GLenum target,
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@ -663,7 +653,7 @@ miptree_create(struct brw_context *brw,
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const GLenum base_format = _mesa_get_format_base_format(format);
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if ((base_format == GL_DEPTH_COMPONENT ||
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base_format == GL_DEPTH_STENCIL) &&
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!force_linear_tiling(layout_flags)) {
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!(layout_flags & MIPTREE_LAYOUT_TILING_NONE)) {
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/* Fix up the Z miptree format for how we're splitting out separate
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* stencil. Gen7 expects there to be no stencil bits in its depth buffer.
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*/
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@ -699,7 +689,8 @@ miptree_create(struct brw_context *brw,
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if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD)
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alloc_flags |= BO_ALLOC_FOR_RENDER;
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isl_tiling_flags_t tiling_flags = force_linear_tiling(layout_flags) ?
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isl_tiling_flags_t tiling_flags =
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(layout_flags & MIPTREE_LAYOUT_TILING_NONE) ?
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ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;
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/* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
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@ -823,7 +814,6 @@ intel_miptree_create_for_bo(struct brw_context *brw,
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/* The BO already has a tiling format and we shouldn't confuse the lower
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* layers by making it try to find a tiling format again.
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*/
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assert((layout_flags & MIPTREE_LAYOUT_TILING_ANY) == 0);
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assert((layout_flags & MIPTREE_LAYOUT_TILING_NONE) == 0);
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mt = make_surface(brw, target, format,
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@ -1059,8 +1049,7 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw,
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struct intel_mipmap_tree *mt;
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uint32_t depth = 1;
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GLenum target = num_samples > 1 ? GL_TEXTURE_2D_MULTISAMPLE : GL_TEXTURE_2D;
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const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
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MIPTREE_LAYOUT_TILING_ANY;
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const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
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mt = intel_miptree_create(brw, target, format, 0, 0,
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width, height, depth, num_samples,
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@ -352,10 +352,7 @@ enum {
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MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
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MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3,
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MIPTREE_LAYOUT_TILING_Y = 1 << 5,
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MIPTREE_LAYOUT_TILING_NONE = 1 << 6,
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MIPTREE_LAYOUT_TILING_ANY = MIPTREE_LAYOUT_TILING_Y |
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MIPTREE_LAYOUT_TILING_NONE,
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};
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struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
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@ -150,7 +150,7 @@ intel_alloc_texture_storage(struct gl_context *ctx,
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0, levels - 1,
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width, height, depth,
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MAX2(num_samples, 1),
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MIPTREE_LAYOUT_TILING_ANY);
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0);
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if (intel_texobj->mt == NULL) {
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return false;
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@ -124,7 +124,7 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
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height,
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depth,
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MAX2(intelImage->base.Base.NumSamples, 1),
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layout_flags | MIPTREE_LAYOUT_TILING_ANY);
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layout_flags);
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}
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static void
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@ -136,8 +136,7 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
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_mesa_get_format_name(firstImage->base.Base.TexFormat),
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width, height, depth, validate_last_level + 1);
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const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
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MIPTREE_LAYOUT_TILING_ANY;
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const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
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intelObj->mt = intel_miptree_create(brw,
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intelObj->base.Target,
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firstImage->base.Base.TexFormat,
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