From 54fa55a3f779fd0b8f373b8d033ccfec1bf97df2 Mon Sep 17 00:00:00 2001 From: Georg Lehmann Date: Wed, 23 Oct 2024 20:28:51 +0200 Subject: [PATCH] radv: don't use v_mqsad_u32_u8 on gfx7 According to tests on hawaii, v_mqsad_u32_u8 always uses saturating accumulation while v_msad_u8 truncates. GFX8+ can control this with the VOP3 clamp bit, on older hardware that's not supported. We want truncation for the NIR opcode. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12062 Fixes: c3c138b10f4 ("radv: optimize msad_4x8 to mqsad_4x8") Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_pipeline.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index fb4206031cb..e4038849f5e 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -569,7 +569,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat NIR_PASS_V(stage->nir, radv_nir_lower_abi, gfx_level, stage, gfx_state, pdev->info.address32_hi); radv_optimize_nir_algebraic( stage->nir, io_to_mem || lowered_ngg || stage->stage == MESA_SHADER_COMPUTE || stage->stage == MESA_SHADER_TASK, - gfx_level >= GFX7); + gfx_level >= GFX8); NIR_PASS(_, stage->nir, nir_lower_fp16_casts, nir_lower_fp16_split_fp64);