From 54d85700a12aa33d185e147c2d5c794ba54b7a11 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 1 Apr 2022 21:47:03 -0400 Subject: [PATCH] radeonsi/gfx11: limit MSAA color buffers to the RGBA channel order Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_state.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 77d855608f6..719ab625c41 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2432,6 +2432,16 @@ static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format if (sample_count > max_eqaa_samples || storage_sample_count > max_samples) return false; } + + /* Gfx11: BGRA doesn't work with samples >= 4. Only allow R/0/1 to be the first + * component for simplicity. + */ + if (sscreen->info.chip_class >= GFX11 && + !util_format_is_depth_or_stencil(format) && + util_format_description(format)->swizzle[0] != PIPE_SWIZZLE_X && + util_format_description(format)->swizzle[0] != PIPE_SWIZZLE_0 && + util_format_description(format)->swizzle[0] != PIPE_SWIZZLE_1) + return false; } if (usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE)) {