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r600: Add support for loading index register from other than chan X

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Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5085>
This commit is contained in:
Gert Wollny 2020-05-06 23:20:49 +02:00 • committed by Marge Bot
parent 3baad03616
commit 54c3d4bd24
2 changed files with 2 additions and 1 deletions
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2
src/gallium/drivers/r600/eg_asm.c
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@ -189,7 +189,7 @@ int egcm_load_index_reg(struct r600_bytecode *bc, unsigned id, bool inside_alu_c
memset(&alu, 0, sizeof(alu));
alu.op = ALU_OP1_MOVA_INT;
alu.src[0].sel = bc->index_reg[id];
alu.src[0].chan = 0;
alu.src[0].chan = bc->index_reg_chan[id];
if (bc->chip_class == CAYMAN)
alu.dst.sel = id == 0 ? CM_V_SQ_MOVA_DST_CF_IDX0 : CM_V_SQ_MOVA_DST_CF_IDX1;

1
src/gallium/drivers/r600/r600_asm.h
View file

@ -278,6 +278,7 @@ struct r600_bytecode {
unsigned r6xx_nop_after_rel_dst;
bool index_loaded[2];
unsigned index_reg[2]; /* indexing register CF_INDEX_[01] */
unsigned index_reg_chan[2]; /* indexing register chanel CF_INDEX_[01] */
unsigned debug_id;
struct r600_isa* isa;
struct r600_bytecode_output pending_outputs[5];