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radeonsi: make si_cp_wait_mem more configurable

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Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
This commit is contained in:
Marek Olšák 2018-12-03 14:58:08 -05:00
parent 9d2c3a1fe0
commit 54bc87469a
5 changed files with 8 additions and 8 deletions
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6
src/gallium/drivers/radeonsi/si_fence.c
View file

@ -160,13 +160,11 @@ unsigned si_cp_write_fence_dwords(struct si_screen *screen)
return dwords;
}
void si_cp_wait_mem(struct si_context *ctx,
void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
uint64_t va, uint32_t ref, uint32_t mask, unsigned flags)
{
struct radeon_cmdbuf *cs = ctx->gfx_cs;
radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1) | flags);
radeon_emit(cs, WAIT_REG_MEM_MEM_SPACE(1) | flags);
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit(cs, ref); /* reference value */

2
src/gallium/drivers/radeonsi/si_perfcounter.c
View file

@ -701,7 +701,7 @@ static void si_pc_emit_stop(struct si_context *sctx,
EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
EOP_DATA_SEL_VALUE_32BIT,
buffer, va, 0, SI_NOT_QUERY);
si_cp_wait_mem(sctx, va, 0, 0xffffffff, 0);
si_cp_wait_mem(sctx, cs, va, 0, 0xffffffff, WAIT_REG_MEM_EQUAL);
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_SAMPLE) | EVENT_INDEX(0));

2
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -1213,7 +1213,7 @@ void si_cp_release_mem(struct si_context *ctx,
struct r600_resource *buf, uint64_t va,
uint32_t new_fence, unsigned query_type);
unsigned si_cp_write_fence_dwords(struct si_screen *screen);
void si_cp_wait_mem(struct si_context *ctx,
void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
void si_init_fence_functions(struct si_context *ctx);
void si_init_screen_fence_functions(struct si_screen *screen);

3
src/gallium/drivers/radeonsi/si_query.c
View file

@ -1576,7 +1576,8 @@ static void si_query_hw_get_result_resource(struct si_context *sctx,
va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size;
va += params.fence_offset;
si_cp_wait_mem(sctx, va, 0x80000000, 0x80000000, 0);
si_cp_wait_mem(sctx, sctx->gfx_cs, va, 0x80000000,
0x80000000, WAIT_REG_MEM_EQUAL);
}
sctx->b.launch_grid(&sctx->b, &grid);

3
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -1056,7 +1056,8 @@ void si_emit_cache_flush(struct si_context *sctx)
EOP_DATA_SEL_VALUE_32BIT,
sctx->wait_mem_scratch, va,
sctx->wait_mem_number, SI_NOT_QUERY);
si_cp_wait_mem(sctx, va, sctx->wait_mem_number, 0xffffffff, 0);
si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
WAIT_REG_MEM_EQUAL);
}
/* Make sure ME is idle (it executes most packets) before continuing.