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synced 2026-05-08 02:38:04 +02:00
freedreno/a6xx: Remove bindfull IBO state
Now that it is unused. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
This commit is contained in:
parent
ce1e73f441
commit
549a8d206a
5 changed files with 1 additions and 111 deletions
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@ -167,8 +167,7 @@ setup_state_map(struct fd_context *ctx)
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fd_context_add_map(ctx, FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK,
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BIT(FD6_GROUP_BLEND));
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fd_context_add_map(ctx, FD_DIRTY_BLEND_COLOR, BIT(FD6_GROUP_BLEND_COLOR));
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fd_context_add_map(ctx, FD_DIRTY_SSBO | FD_DIRTY_IMAGE | FD_DIRTY_PROG,
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BIT(FD6_GROUP_IBO) | BIT(FD6_GROUP_FS_TEX));
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fd_context_add_map(ctx, FD_DIRTY_PROG, BIT(FD6_GROUP_FS_TEX));
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fd_context_add_map(ctx, FD_DIRTY_PROG,
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BIT(FD6_GROUP_VS_TEX) | BIT(FD6_GROUP_HS_TEX) |
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BIT(FD6_GROUP_DS_TEX) | BIT(FD6_GROUP_GS_TEX) |
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@ -583,51 +583,6 @@ build_blend_color(struct fd6_emit *emit) assert_dt
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return ring;
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}
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static struct fd_ringbuffer *
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build_ibo(struct fd6_emit *emit) assert_dt
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{
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struct fd_context *ctx = emit->ctx;
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if (emit->hs) {
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assert(ir3_shader_nibo(emit->hs) == 0);
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assert(ir3_shader_nibo(emit->ds) == 0);
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}
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if (emit->gs) {
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assert(ir3_shader_nibo(emit->gs) == 0);
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}
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unsigned nibo = ir3_shader_nibo(emit->fs);
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if (nibo == 0)
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return NULL;
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struct fd_ringbuffer *ibo_state =
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fd6_build_ibo_state(ctx, emit->fs, PIPE_SHADER_FRAGMENT);
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struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
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ctx->batch->submit, 0x100, FD_RINGBUFFER_STREAMING);
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OUT_PKT7(ring, CP_LOAD_STATE6, 3);
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OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
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CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
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CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
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CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
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CP_LOAD_STATE6_0_NUM_UNIT(nibo));
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OUT_RB(ring, ibo_state);
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OUT_PKT4(ring, REG_A6XX_SP_IBO, 2);
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OUT_RB(ring, ibo_state);
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/* TODO if we used CP_SET_DRAW_STATE for compute shaders, we could
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* de-duplicate this from program->config_stateobj
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*/
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OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
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OUT_RING(ring, nibo);
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fd_ringbuffer_del(ibo_state);
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return ring;
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}
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static void
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fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit) assert_dt
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{
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@ -860,10 +815,6 @@ fd6_emit_3d_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
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state = build_blend_color(emit);
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fd6_state_take_group(&emit->state, state, FD6_GROUP_BLEND_COLOR);
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break;
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case FD6_GROUP_IBO:
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state = build_ibo(emit);
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fd6_state_take_group(&emit->state, state, FD6_GROUP_IBO);
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break;
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case FD6_GROUP_VS_BINDLESS:
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state = fd6_build_bindless_state(ctx, PIPE_SHADER_VERTEX, false);
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fd6_state_take_group(&emit->state, state, FD6_GROUP_VS_BINDLESS);
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@ -960,27 +911,6 @@ fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
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OUT_RING(ring, 0);
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}
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if (dirty & (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
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struct fd_ringbuffer *state =
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fd6_build_ibo_state(ctx, cp, PIPE_SHADER_COMPUTE);
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OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
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OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
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CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
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CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
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CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
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CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(cp)));
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OUT_RB(ring, state);
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OUT_PKT4(ring, REG_A6XX_SP_CS_IBO, 2);
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OUT_RB(ring, state);
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OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
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OUT_RING(ring, ir3_shader_nibo(cp));
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fd_ringbuffer_del(state);
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}
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u_foreach_bit (b, ctx->gen_dirty) {
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enum fd6_state_id group = b;
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@ -65,7 +65,6 @@ enum fd6_state_id {
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FD6_GROUP_SCISSOR,
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FD6_GROUP_BLEND_COLOR,
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FD6_GROUP_SO,
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FD6_GROUP_IBO,
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FD6_GROUP_VS_BINDLESS,
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FD6_GROUP_HS_BINDLESS,
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FD6_GROUP_DS_BINDLESS,
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@ -202,40 +202,6 @@ validate_buffer_descriptor(struct fd_context *ctx, struct fd6_descriptor_set *se
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set->seqno[slot] = rsc->seqno;
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}
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/* Build combined image/SSBO "IBO" state, returns ownership of state reference */
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struct fd_ringbuffer *
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fd6_build_ibo_state(struct fd_context *ctx, const struct ir3_shader_variant *v,
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enum pipe_shader_type shader)
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{
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struct fd_shaderbuf_stateobj *bufso = &ctx->shaderbuf[shader];
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struct fd_shaderimg_stateobj *imgso = &ctx->shaderimg[shader];
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struct fd6_descriptor_set *set = descriptor_set(ctx, shader);
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struct fd_ringbuffer *state = fd_submit_new_ringbuffer(
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ctx->batch->submit,
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ir3_shader_nibo(v) * FDL6_TEX_CONST_DWORDS * 4,
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FD_RINGBUFFER_STREAMING);
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assert(shader == PIPE_SHADER_COMPUTE || shader == PIPE_SHADER_FRAGMENT);
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for (unsigned i = 0; i < v->num_ssbos; i++) {
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unsigned slot = i + IR3_BINDLESS_SSBO_OFFSET;
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validate_buffer_descriptor(ctx, set, slot, &bufso->sb[i]);
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fd6_emit_single_plane_descriptor(state, bufso->sb[i].buffer,
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set->descriptor[slot]);
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}
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for (unsigned i = v->num_ssbos; i < v->num_ibos; i++) {
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unsigned n = i - v->num_ssbos;
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unsigned slot = n + IR3_BINDLESS_IMAGE_OFFSET;
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validate_image_descriptor(ctx, set, slot, &imgso->si[n]);
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fd6_emit_single_plane_descriptor(state, imgso->si[n].resource,
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set->descriptor[slot]);
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}
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return state;
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}
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/* Build bindless descriptor state, returns ownership of state reference */
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struct fd_ringbuffer *
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fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
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@ -35,10 +35,6 @@ void fd6_emit_image_tex(struct fd_context *ctx, struct fd_ringbuffer *ring,
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void fd6_emit_ssbo_tex(struct fd_context *ctx, struct fd_ringbuffer *ring,
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const struct pipe_shader_buffer *pbuf) assert_dt;
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struct ir3_shader_variant;
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struct fd_ringbuffer *
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fd6_build_ibo_state(struct fd_context *ctx, const struct ir3_shader_variant *v,
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enum pipe_shader_type shader) assert_dt;
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struct fd_ringbuffer *
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fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
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bool append_fb_read) assert_dt;
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