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https://gitlab.freedesktop.org/mesa/mesa.git
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nak/sm50: remove ALUSrc and friends
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
This commit is contained in:
Daniel Almeida
Marge Bot
parent
592d8fa436
commit
546edfde83
1 changed files with 101 additions and 284 deletions
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@ -47,28 +47,6 @@ impl Src {
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}
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}
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#[derive(PartialEq, Eq)]
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struct ALURegRef {
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pub reg: RegRef,
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pub abs: bool,
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pub neg: bool,
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}
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#[derive(PartialEq, Eq)]
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struct ALUCBufRef {
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pub cb: CBufRef,
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pub abs: bool,
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pub neg: bool,
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}
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#[derive(PartialEq, Eq)]
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enum ALUSrc {
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None,
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Imm32(u32),
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Reg(ALURegRef),
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CBuf(ALUCBufRef),
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}
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fn src_mod_has_abs(src_mod: SrcMod) -> bool {
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match src_mod {
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SrcMod::None | SrcMod::FNeg | SrcMod::INeg | SrcMod::BNot => false,
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@ -93,81 +71,6 @@ fn src_mod_is_bnot(src_mod: SrcMod) -> bool {
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}
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}
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impl ALUSrc {
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fn is_none(&self) -> bool {
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match self {
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ALUSrc::None => true,
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_ => false,
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}
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}
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fn is_none_or_reg_zero(&self) -> bool {
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match self {
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ALUSrc::None => true,
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ALUSrc::Reg(ALURegRef {
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reg,
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abs: false,
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neg: false,
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}) if reg == &RegRef::zero(RegFile::GPR, 1) => true,
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_ => false,
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}
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}
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fn from_nonzero_src(src: &Src) -> ALUSrc {
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match src.src_ref {
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SrcRef::Reg(reg) => {
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assert!(reg.comps() == 1);
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let alu_ref = ALURegRef {
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reg: reg,
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abs: src_mod_has_abs(src.src_mod),
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neg: src_mod_has_neg(src.src_mod),
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};
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match reg.file() {
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RegFile::GPR => ALUSrc::Reg(alu_ref),
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_ => panic!("Invalid ALU register file"),
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}
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}
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SrcRef::Imm32(i) => {
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assert!(src.src_mod.is_none());
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ALUSrc::Imm32(i)
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}
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SrcRef::CBuf(cb) => {
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let alu_ref = ALUCBufRef {
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cb: cb,
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abs: src_mod_has_abs(src.src_mod),
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neg: src_mod_has_neg(src.src_mod),
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};
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ALUSrc::CBuf(alu_ref)
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}
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_ => panic!("Invalid ALU source"),
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}
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}
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fn zero(file: RegFile) -> ALUSrc {
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let src = Src {
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src_ref: SrcRef::Reg(RegRef::zero(file, 1)),
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/* Modifiers don't matter for zero */
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src_mod: SrcMod::None,
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};
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ALUSrc::from_nonzero_src(&src)
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}
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pub fn from_src(src: &Src) -> ALUSrc {
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match src.src_ref {
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SrcRef::Zero => ALUSrc::zero(RegFile::GPR),
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_ => ALUSrc::from_nonzero_src(src),
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}
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}
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pub fn from_usrc(src: &Src) -> ALUSrc {
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assert!(src.is_uniform());
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match src.src_ref {
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SrcRef::Zero => ALUSrc::zero(RegFile::UGPR),
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_ => ALUSrc::from_nonzero_src(src),
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}
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}
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}
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fn align_down(value: usize, align: usize) -> usize {
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value / align * align
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}
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@ -408,59 +311,6 @@ impl SM50Instr {
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self.set_bit(neg_bit, src.src_mod.is_ineg());
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}
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fn set_alu_reg(
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&mut self,
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range: Range<usize>,
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abs_bit: Option<usize>,
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neg_bit: Option<usize>,
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reg: &ALURegRef,
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) {
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assert!(abs_bit.is_some() || !reg.abs);
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assert!(neg_bit.is_some() || !reg.neg);
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self.set_reg(range, reg.reg);
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if let Some(abs_bit) = abs_bit {
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self.set_bit(abs_bit, reg.abs);
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}
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if let Some(neg_bit) = neg_bit {
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self.set_bit(neg_bit, reg.neg);
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}
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}
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fn set_alu_reg_src(
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&mut self,
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range: Range<usize>,
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abs_bit: Option<usize>,
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neg_bit: Option<usize>,
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src: &ALUSrc,
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) {
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match src {
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ALUSrc::None => (),
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ALUSrc::Reg(reg) => self.set_alu_reg(range, abs_bit, neg_bit, reg),
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_ => panic!("Invalid ALU src0"),
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}
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}
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fn set_alu_cb(
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&mut self,
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range: Range<usize>,
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abs_bit: Option<usize>,
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neg_bit: Option<usize>,
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cb: &ALUCBufRef,
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) {
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self.set_src_cb(range, &cb.cb);
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if let Some(abs_bit) = abs_bit {
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self.set_bit(abs_bit, cb.abs);
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}
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if let Some(neg_bit) = neg_bit {
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self.set_bit(neg_bit, cb.neg);
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}
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}
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fn encode_mov(&mut self, op: &OpMov) {
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match &op.src.src_ref {
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SrcRef::Zero | SrcRef::Reg(_) => {
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@ -487,22 +337,20 @@ impl SM50Instr {
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fn encode_sel(&mut self, op: &OpSel) {
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assert!(op.srcs[1].is_reg_or_zero());
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let alu_src_1 = ALUSrc::from_src(&op.srcs[1]);
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match &alu_src_1 {
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ALUSrc::None => panic!("Invalid source for SEL"),
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ALUSrc::Imm32(imm) => {
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match &op.srcs[1].src_ref {
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SrcRef::Imm32(imm32) => {
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self.set_opcode(0x38a0);
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self.set_src_imm_i20(20..40, 56, *imm);
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self.set_src_imm_i20(20..40, 56, *imm32);
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}
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ALUSrc::Reg(reg) => {
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SrcRef::Zero | SrcRef::Reg(_) => {
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self.set_opcode(0x5ca0);
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self.set_alu_reg_src(20..28, None, None, &alu_src_1);
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self.set_reg_src_ref(20..28, op.srcs[1].src_ref);
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}
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ALUSrc::CBuf(cbuf) => {
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SrcRef::CBuf(cbuf) => {
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self.set_opcode(0x4ca0);
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self.set_alu_cb(20..39, None, None, cbuf);
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self.set_src_cb(20..39, &cbuf);
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}
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src => panic!("Unsupported src type for SEL: {src}"),
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}
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self.set_dst(op.dst);
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@ -750,24 +598,23 @@ impl SM50Instr {
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}
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fn encode_i2f(&mut self, op: &OpI2F) {
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let alu_src = ALUSrc::from_src(&op.src);
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let abs_bit = Some(49);
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let neg_bit = Some(45);
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let abs_bit = 49;
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let neg_bit = 45;
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match &alu_src {
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ALUSrc::None => panic!("Invalid source for I2F"),
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ALUSrc::Imm32(imm) => {
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match &op.src.src_ref {
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SrcRef::Imm32(imm) => {
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self.set_opcode(0x38b8);
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self.set_src_imm_i20(20..40, 56, *imm);
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}
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ALUSrc::Reg(reg) => {
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SrcRef::Zero | SrcRef::Reg(_) => {
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self.set_opcode(0x5cb8);
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self.set_alu_reg_src(20..28, abs_bit, neg_bit, &alu_src);
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self.set_reg_fmod_src(20..28, abs_bit, neg_bit, op.src);
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}
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ALUSrc::CBuf(cbuf) => {
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SrcRef::CBuf(_) => {
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self.set_opcode(0x4cb8);
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self.set_alu_cb(20..39, abs_bit, neg_bit, cbuf);
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self.set_cb_fmod_src(20..39, abs_bit, neg_bit, op.src);
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}
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src => panic!("Unsupported src type for I2F: {src}"),
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}
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self.set_field(41..43, 0_u8); /* TODO: subop */
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@ -782,24 +629,23 @@ impl SM50Instr {
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fn encode_f2f(&mut self, op: &OpF2F) {
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assert!(op.src.is_reg_or_zero());
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let alu_src = ALUSrc::from_src(&op.src);
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let abs_bit = Some(49);
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let neg_bit = Some(45);
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let abs_bit = 49;
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let neg_bit = 45;
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match &alu_src {
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ALUSrc::None => panic!("Invalid source for I2F"),
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ALUSrc::Imm32(imm) => {
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match &op.src.src_ref {
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SrcRef::Imm32(imm) => {
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self.set_opcode(0x38a8);
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self.set_src_imm_i20(20..40, 56, *imm);
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}
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ALUSrc::Reg(reg) => {
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SrcRef::Zero | SrcRef::Reg(_) => {
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self.set_opcode(0x5ca8);
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self.set_alu_reg_src(20..28, abs_bit, neg_bit, &alu_src);
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self.set_reg_fmod_src(20..28, abs_bit, neg_bit, op.src);
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}
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ALUSrc::CBuf(cbuf) => {
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SrcRef::CBuf(_) => {
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self.set_opcode(0x4ca8);
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self.set_alu_cb(20..39, abs_bit, neg_bit, cbuf);
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self.set_cb_fmod_src(20..39, abs_bit, neg_bit, op.src);
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}
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src => panic!("Unsupported src type for F2F: {src}"),
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}
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/* no saturation in the IR, would be bit 50 */
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@ -831,35 +677,36 @@ impl SM50Instr {
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assert!(op.srcs[1].is_reg_or_zero());
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assert!(op.srcs[2].is_reg_or_zero());
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let alu_src_1 = ALUSrc::from_src(&op.srcs[1]);
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let alu_src_2 = ALUSrc::from_src(&op.srcs[2]);
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let neg_0_bit = Some(51);
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let neg_1_bit = Some(51);
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let neg_2_bit = Some(52);
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let neg_0_bit = 51;
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let neg_1_bit = 51;
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let neg_2_bit = 52;
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match &alu_src_2 {
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ALUSrc::None => panic!("Invalid source for IMAD"),
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ALUSrc::Imm32(imm) => panic!("Invalid source for IMAD"),
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ALUSrc::Reg(reg) => match &alu_src_1 {
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ALUSrc::None => panic!("Invalid source for IMAD"),
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ALUSrc::Imm32(imm) => {
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match &op.srcs[2].src_ref {
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SrcRef::Imm32(imm) => {
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panic!("Invalid immediate src2 for IMAD {}", *imm)
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}
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SrcRef::Reg(reg) => match &op.srcs[1].src_ref {
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SrcRef::Imm32(imm) => {
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self.set_opcode(0x3400);
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self.set_src_imm_i20(20..40, 56, *imm);
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}
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ALUSrc::Reg(reg) => {
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SrcRef::Zero | SrcRef::Reg(_) => {
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self.set_opcode(0x5a00);
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self.set_alu_reg_src(20..28, None, neg_1_bit, &alu_src_1);
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self.set_reg_ineg_src(20..28, neg_1_bit, op.srcs[1]);
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}
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ALUSrc::CBuf(cbuf) => {
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SrcRef::CBuf(_) => {
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self.set_opcode(0x4a00);
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self.set_alu_cb(20..39, None, neg_1_bit, cbuf);
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self.set_cb_ineg_src(20..39, neg_1_bit, op.srcs[1]);
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}
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src => panic!("Invalid src1 for IMAD {src}"),
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},
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ALUSrc::CBuf(cbuf) => {
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SrcRef::CBuf(_) => {
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self.set_opcode(0x5200);
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self.set_alu_reg_src(39..47, None, neg_1_bit, &alu_src_1);
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self.set_alu_cb(20..39, None, neg_2_bit, cbuf);
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self.set_reg_ineg_src(39..47, neg_1_bit, op.srcs[1]);
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self.set_cb_ineg_src(20..39, neg_2_bit, op.srcs[2]);
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}
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src => panic!("Unsupported src2 type for F2F: {src}"),
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}
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self.set_bit(48, op.signed); /* src0 signed */
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@ -1399,22 +1246,20 @@ impl SM50Instr {
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fn encode_popc(&mut self, op: &OpPopC) {
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assert!(op.src.is_reg_or_zero());
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let alu_src = ALUSrc::from_src(&op.src);
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match &alu_src {
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ALUSrc::None => panic!("Invalid source for POPC"),
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ALUSrc::Imm32(imm) => {
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match &op.src.src_ref {
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SrcRef::Imm32(imm) => {
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self.set_opcode(0x3808);
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self.set_src_imm_i20(20..40, 56, *imm);
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}
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ALUSrc::Reg(reg) => {
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SrcRef::Reg(_) => {
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self.set_opcode(0x5c08);
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self.set_alu_reg_src(20..28, None, None, &alu_src);
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self.set_reg_src(20..28, op.src);
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}
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ALUSrc::CBuf(cbuf) => {
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SrcRef::CBuf(cbuf) => {
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self.set_opcode(0x4c08);
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self.set_alu_cb(20..39, None, None, cbuf);
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self.set_src_cb(20..39, cbuf);
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}
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src => panic!("Invalid source for POPC: {src}"),
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}
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let not_mod = matches!(op.src.src_mod, SrcMod::BNot);
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@ -1461,25 +1306,23 @@ impl SM50Instr {
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assert!(op.srcs[0].is_reg_or_zero());
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assert!(op.srcs[1].is_reg_or_zero());
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let alu_src_1 = ALUSrc::from_src(&op.srcs[1]);
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let alu_src_0 = ALUSrc::from_src(&op.srcs[0]);
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match &alu_src_1 {
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ALUSrc::None => panic!("Invalid source for FMNMX"),
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ALUSrc::Imm32(imm32) => {
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match &op.srcs[1].src_ref {
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SrcRef::Imm32(imm32) => {
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self.set_opcode(0x3860);
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self.set_src_imm_f20(20..40, 56, *imm32);
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}
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ALUSrc::Reg(reg) => {
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SrcRef::Zero | SrcRef::Reg(_) => {
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self.set_opcode(0x5c60);
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self.set_alu_reg_src(20..28, Some(49), Some(45), &alu_src_1);
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self.set_reg_fmod_src(20..28, 49, 45, op.srcs[1]);
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}
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ALUSrc::CBuf(cbuf) => {
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SrcRef::CBuf(_) => {
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self.set_opcode(0x4c60);
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self.set_alu_cb(20..39, Some(49), Some(45), cbuf);
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self.set_cb_fmod_src(20..39, 49, 45, op.srcs[1]);
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}
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src => panic!("Unsupported src type for FMNMX: {src}"),
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}
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self.set_alu_reg_src(8..16, Some(46), Some(48), &alu_src_0);
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self.set_reg_fmod_src(8..16, 46, 48, op.srcs[0]);
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self.set_dst(op.dst);
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self.set_pred_src(39..42, 42, op.min);
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self.set_bit(44, false); /* TODO: FMZ */
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@ -1489,9 +1332,6 @@ impl SM50Instr {
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assert!(op.srcs[0].is_reg_or_zero());
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assert!(op.srcs[1].is_reg_or_zero());
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let alu_src_1 = ALUSrc::from_src(&op.srcs[1]);
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let alu_src_0 = ALUSrc::from_src(&op.srcs[0]);
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if let Some(imm32) = op.srcs[1].as_imm_not_f20() {
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self.set_opcode(0x1e00);
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@ -1505,20 +1345,20 @@ impl SM50Instr {
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^ src_mod_has_neg(op.srcs[1].src_mod),
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);
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} else {
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match &alu_src_1 {
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ALUSrc::None => panic!("Invalid source for FMUL"),
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ALUSrc::Imm32(imm32) => {
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match &op.srcs[1].src_ref {
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SrcRef::Imm32(imm32) => {
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self.set_opcode(0x3868);
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self.set_src_imm_f20(20..40, 56, *imm32);
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}
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ALUSrc::Reg(_) => {
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SrcRef::Zero | SrcRef::Reg(_) => {
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self.set_opcode(0x5c68);
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self.set_alu_reg_src(20..28, None, None, &alu_src_1);
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self.set_reg_src(20..28, op.srcs[1]);
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}
|
||||
ALUSrc::CBuf(cbuf) => {
|
||||
SrcRef::CBuf(cbuf) => {
|
||||
self.set_opcode(0x4c68);
|
||||
self.set_alu_cb(20..39, None, None, cbuf);
|
||||
self.set_src_cb(20..39, cbuf);
|
||||
}
|
||||
src => panic!("Unsupported src type for FMUL: {src}"),
|
||||
}
|
||||
|
||||
self.set_rnd_mode(39..41, op.rnd_mode);
|
||||
|
|
@ -1533,7 +1373,7 @@ impl SM50Instr {
|
|||
self.set_bit(50, op.saturate);
|
||||
}
|
||||
|
||||
self.set_alu_reg_src(8..16, Some(46), Some(48), &alu_src_0);
|
||||
self.set_reg_fmod_src(8..16, 46, 48, op.srcs[0]);
|
||||
self.set_dst(op.dst);
|
||||
}
|
||||
|
||||
|
|
@ -1564,26 +1404,23 @@ impl SM50Instr {
|
|||
assert!(op.srcs[0].is_reg_or_zero());
|
||||
assert!(op.srcs[1].is_reg_or_zero());
|
||||
|
||||
let alu_src_1 = ALUSrc::from_src(&op.srcs[1]);
|
||||
let alu_src_0 = ALUSrc::from_src(&op.srcs[0]);
|
||||
|
||||
match &alu_src_1 {
|
||||
ALUSrc::None => panic!("Invalid source for FSET"),
|
||||
ALUSrc::Imm32(imm32) => {
|
||||
match &op.srcs[1].src_ref {
|
||||
SrcRef::Imm32(imm32) => {
|
||||
self.set_opcode(0x3000);
|
||||
self.set_src_imm_f20(20..40, 56, *imm32);
|
||||
}
|
||||
ALUSrc::Reg(reg) => {
|
||||
SrcRef::Zero | SrcRef::Reg(_) => {
|
||||
self.set_opcode(0x5800);
|
||||
self.set_alu_reg_src(20..28, Some(44), Some(53), &alu_src_1);
|
||||
self.set_reg_fmod_src(20..28, 44, 53, op.srcs[1]);
|
||||
}
|
||||
ALUSrc::CBuf(cbuf) => {
|
||||
SrcRef::CBuf(_) => {
|
||||
self.set_opcode(0x4800);
|
||||
self.set_alu_cb(20..39, Some(44), Some(6), cbuf);
|
||||
self.set_cb_fmod_src(20..39, 44, 6, op.srcs[1]);
|
||||
}
|
||||
src => panic!("Unsupported src type for FSET: {src}"),
|
||||
}
|
||||
|
||||
self.set_alu_reg_src(8..16, Some(54), Some(43), &alu_src_0);
|
||||
self.set_reg_fmod_src(8..16, 54, 43, op.srcs[0]);
|
||||
self.set_pred_src(39..42, 42, SrcRef::True.into());
|
||||
self.set_float_cmp_op(48..52, op.cmp_op);
|
||||
self.set_bit(52, true); /* bool float */
|
||||
|
|
@ -1594,22 +1431,20 @@ impl SM50Instr {
|
|||
fn encode_fsetp(&mut self, op: &OpFSetP) {
|
||||
assert!(op.srcs[0].is_reg_or_zero());
|
||||
|
||||
let alu_src_1 = ALUSrc::from_src(&op.srcs[1]);
|
||||
let alu_src_0 = ALUSrc::from_src(&op.srcs[0]);
|
||||
match &alu_src_1 {
|
||||
ALUSrc::None => panic!("Invalid source for FADD"),
|
||||
ALUSrc::Imm32(imm32) => {
|
||||
match &op.srcs[1].src_ref {
|
||||
SrcRef::Imm32(imm32) => {
|
||||
self.set_opcode(0x36b0);
|
||||
self.set_src_imm_f20(20..40, 56, *imm32);
|
||||
}
|
||||
ALUSrc::Reg(reg) => {
|
||||
SrcRef::Zero | SrcRef::Reg(_) => {
|
||||
self.set_opcode(0x5bb0);
|
||||
self.set_alu_reg_src(20..28, Some(44), Some(6), &alu_src_1);
|
||||
self.set_reg_fmod_src(20..28, 44, 6, op.srcs[1]);
|
||||
}
|
||||
ALUSrc::CBuf(cbuf) => {
|
||||
SrcRef::CBuf(_) => {
|
||||
self.set_opcode(0x4bb0);
|
||||
self.set_alu_cb(20..39, Some(44), Some(6), cbuf);
|
||||
self.set_cb_fmod_src(20..39, 44, 6, op.srcs[1]);
|
||||
}
|
||||
src => panic!("Unsupported src type for FSETP: {src}"),
|
||||
}
|
||||
|
||||
self.set_pred_dst(3..6, op.dst);
|
||||
|
|
@ -1618,7 +1453,7 @@ impl SM50Instr {
|
|||
self.set_pred_set_op(45..47, op.set_op);
|
||||
self.set_bit(47, false); /* TODO: Denorm mode */
|
||||
self.set_float_cmp_op(48..52, op.cmp_op);
|
||||
self.set_alu_reg_src(8..16, Some(7), Some(43), &alu_src_0);
|
||||
self.set_reg_fmod_src(8..16, 7, 43, op.srcs[0]);
|
||||
}
|
||||
|
||||
fn encode_mufu(&mut self, op: &OpMuFu) {
|
||||
|
|
@ -1628,12 +1463,7 @@ impl SM50Instr {
|
|||
self.set_opcode(0x5080);
|
||||
|
||||
self.set_dst(op.dst);
|
||||
self.set_alu_reg_src(
|
||||
8..16,
|
||||
Some(46),
|
||||
Some(48),
|
||||
&ALUSrc::from_src(&op.src),
|
||||
);
|
||||
self.set_reg_fmod_src(8..16, 46, 48, op.src);
|
||||
|
||||
self.set_field(
|
||||
20..24,
|
||||
|
|
@ -1659,32 +1489,24 @@ impl SM50Instr {
|
|||
|
||||
// IABS isn't a thing on SM50, we use I2I instead.
|
||||
|
||||
// Enforce ABS
|
||||
let mut src1 = ALUSrc::from_src(&op.src);
|
||||
match &mut src1 {
|
||||
ALUSrc::Reg(reg) => reg.abs = true,
|
||||
ALUSrc::CBuf(cbuf) => cbuf.abs = true,
|
||||
_ => {}
|
||||
}
|
||||
|
||||
// We always assume 32bits signed for now
|
||||
let src_type = IntType::I32;
|
||||
let dst_type = IntType::I32;
|
||||
|
||||
match &src1 {
|
||||
ALUSrc::None => panic!("Invalid source for IABS"),
|
||||
ALUSrc::Imm32(imm32) => {
|
||||
match &op.src.src_ref {
|
||||
SrcRef::Imm32(imm32) => {
|
||||
self.set_opcode(0x38e0);
|
||||
self.set_src_imm_f20(20..40, 56, *imm32);
|
||||
}
|
||||
ALUSrc::Reg(reg) => {
|
||||
SrcRef::Zero | SrcRef::Reg(_) => {
|
||||
self.set_opcode(0x5ce0);
|
||||
self.set_alu_reg_src(20..28, Some(45), Some(49), &src1);
|
||||
self.set_reg_fmod_src(20..28, 45, 49, op.src);
|
||||
}
|
||||
ALUSrc::CBuf(cbuf) => {
|
||||
SrcRef::CBuf(_) => {
|
||||
self.set_opcode(0x4ce0);
|
||||
self.set_alu_cb(20..39, Some(45), Some(49), cbuf);
|
||||
self.set_cb_fmod_src(20..39, 45, 49, op.src);
|
||||
}
|
||||
src => panic!("Unsupported src type for IABS: {src}"),
|
||||
}
|
||||
self.set_bit(12, dst_type.is_signed());
|
||||
self.set_bit(13, src_type.is_signed());
|
||||
|
|
@ -1744,29 +1566,24 @@ impl SM50Instr {
|
|||
assert!(op.sel.is_reg_or_zero());
|
||||
assert!(op.srcs[1].is_reg_or_zero());
|
||||
|
||||
/* TODO: is src[1] in codegen op.srcs[1] or op.selection? */
|
||||
let alu_src_1 = ALUSrc::from_src(&op.srcs[1]);
|
||||
let alu_src_0 = ALUSrc::from_src(&op.srcs[0]);
|
||||
let sel = ALUSrc::from_src(&op.sel);
|
||||
|
||||
match &alu_src_1 {
|
||||
ALUSrc::None => panic!("Invalid source for IADD2"),
|
||||
ALUSrc::Imm32(imm) => {
|
||||
match &op.sel.src_ref {
|
||||
SrcRef::Imm32(imm) => {
|
||||
self.set_opcode(0x36c0);
|
||||
self.set_src_imm_i20(20..40, 56, *imm);
|
||||
}
|
||||
ALUSrc::Reg(reg) => {
|
||||
SrcRef::Zero | SrcRef::Reg(_) => {
|
||||
self.set_opcode(0x5bc0);
|
||||
self.set_alu_reg_src(20..28, None, None, &alu_src_1);
|
||||
self.set_reg_src(20..28, op.sel);
|
||||
}
|
||||
ALUSrc::CBuf(cbuf) => {
|
||||
SrcRef::CBuf(cbuf) => {
|
||||
self.set_opcode(0x4bc0);
|
||||
self.set_alu_cb(20..39, None, None, cbuf);
|
||||
self.set_src_cb(20..39, cbuf);
|
||||
}
|
||||
src => panic!("Unsupported src type for PRMT: {src}"),
|
||||
}
|
||||
|
||||
self.set_alu_reg_src(8..16, None, None, &alu_src_0);
|
||||
self.set_alu_reg_src(39..47, None, None, &sel);
|
||||
self.set_reg_src(8..16, op.srcs[0]);
|
||||
self.set_reg_src(39..47, op.srcs[1]);
|
||||
self.set_dst(op.dst);
|
||||
/* TODO: subop? */
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue