From 54630d224c9d6ae809e71b07e1d6c175c059d248 Mon Sep 17 00:00:00 2001 From: Rohan Garg Date: Mon, 16 Sep 2024 16:07:03 +0200 Subject: [PATCH] intel/compiler: use the correct cache enum for loads and stores Fixes: 74efde7 ('intel/brw/xehp+: Drop redundant arguments of lsc_msg_desc*()') Signed-off-by: Rohan Garg Reviewed-by: Lionel Landwerlin Part-of: (cherry picked from commit daea7e1651dc1d43e645ac3b9d867767257e014d) --- .pick_status.json | 2 +- src/intel/compiler/brw_lower_logical_sends.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index f4514c66f82..1807f0d11ee 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -74,7 +74,7 @@ "description": "intel/compiler: use the correct cache enum for loads and stores", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "74efde76635ca0cbd582b6ca3ab4bb5a24b9d2fe", "notes": null diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index 316a76d1090..d0941565451 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -114,7 +114,7 @@ lower_urb_read_logical_send_xe2(const fs_builder &bld, fs_inst *inst) LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A32, LSC_DATA_SIZE_D32, dst_comps /* num_channels */, false /* transpose */, - LSC_CACHE(devinfo, STORE, L1UC_L3UC)); + LSC_CACHE(devinfo, LOAD, L1UC_L3UC)); /* Update the original instruction. */ inst->opcode = SHADER_OPCODE_SEND;