From 545509553a72a4634bde0e65915ee4b33f5f3b3b Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 12 Feb 2026 10:25:05 +0100 Subject: [PATCH] radv/meta: fix depth/stencil resolves with different regions This is possible since VK_KHR_maintenance10. This fixes new VKCTS coverage in dEQP-VK.pipeline.*.multisample.m10_resolve.*. Cc: mesa-stable Signed-off-by: Samuel Pitoiset (cherry picked from commit ab6147e8ef79e58b955876083ef71d665ae2d19b) Part-of: --- .pick_status.json | 2 +- src/amd/vulkan/meta/radv_meta_resolve_cs.c | 4 +++- src/amd/vulkan/meta/radv_meta_resolve_fs.c | 16 ++++++++++++++++ src/amd/vulkan/nir/radv_meta_nir.c | 21 ++++++++++++--------- 4 files changed, 32 insertions(+), 11 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 8bd00811a86..0e2f06b1602 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -844,7 +844,7 @@ "description": "radv/meta: fix depth/stencil resolves with different regions", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null diff --git a/src/amd/vulkan/meta/radv_meta_resolve_cs.c b/src/amd/vulkan/meta/radv_meta_resolve_cs.c index df815ed17f1..d91a42b61e6 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/meta/radv_meta_resolve_cs.c @@ -467,7 +467,9 @@ radv_meta_resolve_depth_stencil_cs(struct radv_cmd_buffer *cmd_buffer, struct ra radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); - const uint32_t push_constants[2] = {region->srcOffset.x, region->srcOffset.y}; + const uint32_t push_constants[5] = { + region->srcOffset.x, region->srcOffset.y, region->dstOffset.x, region->dstOffset.y, region->dstOffset.z, + }; const VkPushConstantsInfoKHR pc_info = { .sType = VK_STRUCTURE_TYPE_PUSH_CONSTANTS_INFO_KHR, diff --git a/src/amd/vulkan/meta/radv_meta_resolve_fs.c b/src/amd/vulkan/meta/radv_meta_resolve_fs.c index a7eb1b24e12..1f9c7110317 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve_fs.c +++ b/src/amd/vulkan/meta/radv_meta_resolve_fs.c @@ -679,6 +679,22 @@ radv_meta_resolve_depth_stencil_fs(struct radv_cmd_buffer *cmd_buffer, struct ra radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &resolve_area); + const uint32_t push_constants[2] = { + region->srcOffset.x - region->dstOffset.x, + region->srcOffset.y - region->dstOffset.y, + }; + + const VkPushConstantsInfoKHR push_constants_info = { + .sType = VK_STRUCTURE_TYPE_PUSH_CONSTANTS_INFO, + .layout = layout, + .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT, + .offset = 0, + .size = sizeof(push_constants), + .pValues = push_constants, + }; + + radv_CmdPushConstants2(radv_cmd_buffer_to_handle(cmd_buffer), &push_constants_info); + radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0); const VkRenderingEndInfoKHR end_info = { diff --git a/src/amd/vulkan/nir/radv_meta_nir.c b/src/amd/vulkan/nir/radv_meta_nir.c index 20a68b4e5db..2e9fc63a476 100644 --- a/src/amd/vulkan/nir/radv_meta_nir.c +++ b/src/amd/vulkan/nir/radv_meta_nir.c @@ -1395,19 +1395,21 @@ radv_meta_nir_build_depth_stencil_resolve_compute_shader(struct radv_device *dev nir_def *global_id = radv_meta_nir_get_global_ids(&b, 3); - nir_def *offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8); + nir_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8); + nir_def *dst_offset = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 8), .range = 20); - nir_def *resolve_coord = nir_iadd(&b, nir_trim_vector(&b, global_id, 2), offset); + nir_def *src_coord = nir_iadd(&b, nir_trim_vector(&b, global_id, 2), src_offset); + nir_def *dst_coord = nir_iadd(&b, global_id, dst_offset); - nir_def *img_coord = - nir_vec3(&b, nir_channel(&b, resolve_coord, 0), nir_channel(&b, resolve_coord, 1), nir_channel(&b, global_id, 2)); + nir_def *src_img_coord = + nir_vec3(&b, nir_channel(&b, src_coord, 0), nir_channel(&b, src_coord, 1), nir_channel(&b, global_id, 2)); nir_deref_instr *input_img_deref = nir_build_deref_var(&b, input_img); - nir_def *outval = nir_txf_ms(&b, img_coord, nir_imm_int(&b, 0), .texture_deref = input_img_deref); + nir_def *outval = nir_txf_ms(&b, src_img_coord, nir_imm_int(&b, 0), .texture_deref = input_img_deref); if (resolve_mode != VK_RESOLVE_MODE_SAMPLE_ZERO_BIT) { for (int i = 1; i < samples; i++) { - nir_def *si = nir_txf_ms(&b, img_coord, nir_imm_int(&b, i), .texture_deref = input_img_deref); + nir_def *si = nir_txf_ms(&b, src_img_coord, nir_imm_int(&b, i), .texture_deref = input_img_deref); switch (resolve_mode) { case VK_RESOLVE_MODE_AVERAGE_BIT: @@ -1435,8 +1437,8 @@ radv_meta_nir_build_depth_stencil_resolve_compute_shader(struct radv_device *dev outval = nir_fdiv_imm(&b, outval, samples); } - nir_def *coord = nir_vec4(&b, nir_channel(&b, img_coord, 0), nir_channel(&b, img_coord, 1), - nir_channel(&b, img_coord, 2), nir_undef(&b, 1, 32)); + nir_def *coord = nir_vec4(&b, nir_channel(&b, dst_coord, 0), nir_channel(&b, dst_coord, 1), + nir_channel(&b, dst_coord, 2), nir_undef(&b, 1, 32)); nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->def, coord, nir_undef(&b, 1, 32), outval, nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_2D, .image_array = true); return b.shader; @@ -1495,10 +1497,11 @@ radv_meta_nir_build_depth_stencil_resolve_fragment_shader(struct radv_device *de fs_out->data.location = index == RADV_META_DEPTH_RESOLVE ? FRAG_RESULT_DEPTH : FRAG_RESULT_STENCIL; nir_def *pos_in = nir_trim_vector(&b, nir_load_frag_coord(&b), 2); + nir_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8); nir_def *pos_int = nir_f2i32(&b, pos_in); - nir_def *img_coord = nir_trim_vector(&b, pos_int, 2); + nir_def *img_coord = nir_trim_vector(&b, nir_iadd(&b, pos_int, src_offset), 2); nir_deref_instr *input_img_deref = nir_build_deref_var(&b, input_img); nir_def *outval = nir_txf_ms(&b, img_coord, nir_imm_int(&b, 0), .texture_deref = input_img_deref);