diff --git a/src/gallium/drivers/crocus/crocus_bufmgr.c b/src/gallium/drivers/crocus/crocus_bufmgr.c
index 357ea98b2cd..62333703996 100644
--- a/src/gallium/drivers/crocus/crocus_bufmgr.c
+++ b/src/gallium/drivers/crocus/crocus_bufmgr.c
@@ -51,7 +51,7 @@
 #include <time.h>
 
 #include "errno.h"
-#include "common/intel_clflush.h"
+#include "common/intel_mem.h"
 #include "dev/intel_debug.h"
 #include "common/intel_gem.h"
 #include "dev/intel_device_info.h"
diff --git a/src/gallium/drivers/iris/iris_bufmgr.c b/src/gallium/drivers/iris/iris_bufmgr.c
index fd4f01e6cc9..a00203cfaeb 100644
--- a/src/gallium/drivers/iris/iris_bufmgr.c
+++ b/src/gallium/drivers/iris/iris_bufmgr.c
@@ -49,7 +49,7 @@
 
 #include "errno.h"
 #include "common/intel_aux_map.h"
-#include "common/intel_clflush.h"
+#include "common/intel_mem.h"
 #include "dev/intel_debug.h"
 #include "common/intel_gem.h"
 #include "dev/intel_device_info.h"
diff --git a/src/intel/common/intel_clflush.h b/src/intel/common/intel_mem.c
similarity index 93%
rename from src/intel/common/intel_clflush.h
rename to src/intel/common/intel_mem.c
index a4f33cbe1eb..8d8452db76f 100644
--- a/src/intel/common/intel_clflush.h
+++ b/src/intel/common/intel_mem.c
@@ -21,14 +21,12 @@
  * IN THE SOFTWARE.
  */
 
-#ifndef INTEL_CLFLUSH_H
-#define INTEL_CLFLUSH_H
+#include "intel_mem.h"
 
-#define CACHELINE_SIZE 64
-#define CACHELINE_MASK 63
+#include <stdint.h>
 
 #ifdef SUPPORT_INTEL_INTEGRATED_GPUS
-static inline void
+void
 intel_clflush_range(void *start, size_t size)
 {
    void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
@@ -40,14 +38,14 @@ intel_clflush_range(void *start, size_t size)
    }
 }
 
-static inline void
+void
 intel_flush_range(void *start, size_t size)
 {
    __builtin_ia32_mfence();
    intel_clflush_range(start, size);
 }
 
-static inline void
+void
 intel_invalidate_range(void *start, size_t size)
 {
    if (size == 0)
@@ -69,5 +67,3 @@ intel_invalidate_range(void *start, size_t size)
    __builtin_ia32_mfence();
 }
 #endif /* SUPPORT_INTEL_INTEGRATED_GPUS */
-
-#endif
diff --git a/src/intel/common/intel_mem.h b/src/intel/common/intel_mem.h
new file mode 100644
index 00000000000..599995d4d01
--- /dev/null
+++ b/src/intel/common/intel_mem.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef INTEL_MEM_H
+#define INTEL_MEM_H
+
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CACHELINE_SIZE 64
+#define CACHELINE_MASK 63
+
+#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
+void intel_clflush_range(void *start, size_t size);
+void intel_flush_range(void *start, size_t size);
+void intel_invalidate_range(void *start, size_t size);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* INTEL_MEM_H */
diff --git a/src/intel/common/meson.build b/src/intel/common/meson.build
index ec6ae6ce20e..bc71a27dd18 100644
--- a/src/intel/common/meson.build
+++ b/src/intel/common/meson.build
@@ -32,7 +32,6 @@ files_libintel_common = files(
   'intel_aux_map.c',
   'intel_aux_map.h',
   'intel_buffer_alloc.h',
-  'intel_clflush.h',
   'intel_decoder.h',
   'intel_disasm.c',
   'intel_disasm.h',
@@ -51,6 +50,8 @@ files_libintel_common = files(
   'intel_uuid.h',
   'intel_measure.c',
   'intel_measure.h',
+  'intel_mem.c',
+  'intel_mem.h',
   'intel_pixel_hash.h'
 )
 
diff --git a/src/intel/tools/intel_sanitize_gpu.c b/src/intel/tools/intel_sanitize_gpu.c
index 827f5ba7909..a3332507090 100644
--- a/src/intel/tools/intel_sanitize_gpu.c
+++ b/src/intel/tools/intel_sanitize_gpu.c
@@ -43,7 +43,7 @@
 
 #define MESA_LOG_TAG "INTEL-SANITIZE-GPU"
 #include "util/log.h"
-#include "common/intel_clflush.h"
+#include "common/intel_mem.h"
 
 static int (*libc_open)(const char *pathname, int flags, mode_t mode);
 static int (*libc_close)(int fd);
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index c990d94bf45..3d8bb373771 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -41,12 +41,12 @@
 #define VG(x) ((void)0)
 #endif
 
-#include "common/intel_clflush.h"
 #include "common/intel_decoder.h"
 #include "common/intel_engine.h"
 #include "common/intel_gem.h"
 #include "common/intel_l3_config.h"
 #include "common/intel_measure.h"
+#include "common/intel_mem.h"
 #include "common/intel_sample_positions.h"
 #include "dev/intel_device_info.h"
 #include "blorp/blorp.h"
diff --git a/src/intel/vulkan_hasvk/anv_private.h b/src/intel/vulkan_hasvk/anv_private.h
index a632bd57df9..663f3ccc9a0 100644
--- a/src/intel/vulkan_hasvk/anv_private.h
+++ b/src/intel/vulkan_hasvk/anv_private.h
@@ -41,12 +41,12 @@
 #define VG(x) ((void)0)
 #endif
 
-#include "common/intel_clflush.h"
 #include "common/intel_decoder.h"
 #include "common/intel_engine.h"
 #include "common/intel_gem.h"
 #include "common/intel_l3_config.h"
 #include "common/intel_measure.h"
+#include "common/intel_mem.h"
 #include "common/intel_sample_positions.h"
 #include "dev/intel_device_info.h"
 #include "blorp/blorp.h"