diff --git a/src/imagination/vulkan/pvr_cmd_buffer.c b/src/imagination/vulkan/pvr_cmd_buffer.c index 509a180c1fc..b19221bbedd 100644 --- a/src/imagination/vulkan/pvr_cmd_buffer.c +++ b/src/imagination/vulkan/pvr_cmd_buffer.c @@ -37,6 +37,7 @@ #include "pvr_device_info.h" #include "pvr_end_of_tile.h" #include "pvr_formats.h" +#include "pvr_hardcode.h" #include "pvr_hw_pass.h" #include "pvr_job_common.h" #include "pvr_job_render.h" @@ -2968,7 +2969,7 @@ pvr_setup_vertex_buffers(struct pvr_cmd_buffer *cmd_buffer, return VK_SUCCESS; } -static VkResult pvr_setup_descriptor_mappings( +static VkResult pvr_setup_descriptor_mappings_old( struct pvr_cmd_buffer *const cmd_buffer, enum pvr_stage_allocation stage, const struct pvr_stage_allocation_descriptor_state *descriptor_state, @@ -3205,6 +3206,37 @@ static VkResult pvr_setup_descriptor_mappings( return VK_SUCCESS; } +static VkResult +pvr_setup_descriptor_mappings_new(uint32_t *const descriptor_data_offset_out) +{ + *descriptor_data_offset_out = ~0; + + pvr_finishme("Implement new desc set path."); + + return VK_ERROR_UNKNOWN; +} + +static VkResult pvr_setup_descriptor_mappings( + struct pvr_cmd_buffer *const cmd_buffer, + enum pvr_stage_allocation stage, + const struct pvr_stage_allocation_descriptor_state *descriptor_state, + const pvr_dev_addr_t *const num_worgroups_buff_addr, + uint32_t *const descriptor_data_offset_out) +{ + const bool old_path = + pvr_hard_code_shader_required(&cmd_buffer->device->pdevice->dev_info); + + if (old_path) { + return pvr_setup_descriptor_mappings_old(cmd_buffer, + stage, + descriptor_state, + num_worgroups_buff_addr, + descriptor_data_offset_out); + } + + return pvr_setup_descriptor_mappings_new(descriptor_data_offset_out); +} + static void pvr_compute_update_shared(struct pvr_cmd_buffer *cmd_buffer, struct pvr_sub_cmd_compute *const sub_cmd) { diff --git a/src/imagination/vulkan/pvr_pipeline.c b/src/imagination/vulkan/pvr_pipeline.c index e97459eca78..9975a4a682e 100644 --- a/src/imagination/vulkan/pvr_pipeline.c +++ b/src/imagination/vulkan/pvr_pipeline.c @@ -656,52 +656,60 @@ static VkResult pvr_pds_descriptor_program_create_and_upload( uint32_t *staging_buffer; VkResult result; + const bool old_path = + pvr_hard_code_shader_required(&device->pdevice->dev_info); + assert(stage != PVR_STAGE_ALLOCATION_COUNT); *pds_info = (struct pvr_pds_info){ 0 }; - result = pvr_pds_descriptor_program_setup_buffers( - device, - device->features.robustBufferAccess, - compile_time_consts_data, - ubo_data, - &program.buffers, - &program.buffer_count, - &descriptor_state->static_consts); - if (result != VK_SUCCESS) - return result; + if (old_path) { + result = pvr_pds_descriptor_program_setup_buffers( + device, + device->features.robustBufferAccess, + compile_time_consts_data, + ubo_data, + &program.buffers, + &program.buffer_count, + &descriptor_state->static_consts); + if (result != VK_SUCCESS) + return result; - if (layout->per_stage_reg_info[stage].primary_dynamic_size_in_dwords) - assert(!"Unimplemented"); + if (layout->per_stage_reg_info[stage].primary_dynamic_size_in_dwords) + assert(!"Unimplemented"); - for (uint32_t set_num = 0; set_num < layout->set_count; set_num++) { - const struct pvr_descriptor_set_layout_mem_layout *const reg_layout = - &layout->register_layout_in_dwords_per_stage[stage][set_num]; - const uint32_t start_offset = explicit_const_usage->start_offset; + for (uint32_t set_num = 0; set_num < layout->set_count; set_num++) { + const struct pvr_descriptor_set_layout_mem_layout *const reg_layout = + &layout->register_layout_in_dwords_per_stage[stage][set_num]; + const uint32_t start_offset = explicit_const_usage->start_offset; - /* TODO: Use compiler usage info to optimize this? */ + /* TODO: Use compiler usage info to optimize this? */ + + /* Only dma primaries if they are actually required. */ + if (reg_layout->primary_size) { + program.descriptor_sets[program.descriptor_set_count++] = + (struct pvr_pds_descriptor_set){ + .descriptor_set = set_num, + .size_in_dwords = reg_layout->primary_size, + .destination = reg_layout->primary_offset + start_offset, + .primary = true, + }; + } + + /* Only dma secondaries if they are actually required. */ + if (!reg_layout->secondary_size) + continue; - /* Only dma primaries if they are actually required. */ - if (reg_layout->primary_size) { program.descriptor_sets[program.descriptor_set_count++] = (struct pvr_pds_descriptor_set){ .descriptor_set = set_num, - .size_in_dwords = reg_layout->primary_size, - .destination = reg_layout->primary_offset + start_offset, - .primary = true, + .size_in_dwords = reg_layout->secondary_size, + .destination = reg_layout->secondary_offset + start_offset, }; } - - /* Only dma secondaries if they are actually required. */ - if (!reg_layout->secondary_size) - continue; - - program.descriptor_sets[program.descriptor_set_count++] = - (struct pvr_pds_descriptor_set){ - .descriptor_set = set_num, - .size_in_dwords = reg_layout->secondary_size, - .destination = reg_layout->secondary_offset + start_offset, - }; + } else { + pvr_finishme("Implement new desc set path."); + return VK_ERROR_UNKNOWN; } entries_buffer = vk_alloc2(&device->vk.alloc,