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synced 2026-05-01 03:48:06 +02:00
- Remove one of the loops in emit_arith
- Handle REPL_ALPHA in emit_arith (possibly incorrect for some things) - Start on getting demos/arbfplight.c to look right. Won't be animated yet, need to re-work const emit so we can update consts without re-translating the entire program. Assertion in r300_state.c::setup_rs_unit needs to be disabled for it to work.
This commit is contained in:
Ben Skeggs
parent
f387c83ec1
commit
53d13e014f
3 changed files with 134 additions and 56 deletions
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@ -38,6 +38,8 @@
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* - Reuse input/temp regs, if they're no longer needed.
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* - Find out whether there's any benifit in ordering registers the way
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* fglrx does (see r300_reg.h).
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* - Verify results of opcodes for accuracy, I've only checked them
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* in specific cases.
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* - and more...
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*/
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@ -78,11 +80,11 @@ const struct {
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{ "MAX", 2, R300_FPI0_OUTC_MAX, R300_FPI2_OUTA_MAX },
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{ "CMP", 3, R300_FPI0_OUTC_CMP, R300_FPI2_OUTA_CMP },
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{ "FRC", 1, R300_FPI0_OUTC_FRC, R300_FPI2_OUTA_FRC },
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/* should the vector insns below be REPL_ALPHA? */
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{ "EX2", 1, PFS_INVAL, R300_FPI2_OUTA_EX2 },
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{ "LG2", 1, PFS_INVAL, R300_FPI2_OUTA_LG2 },
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{ "RCP", 1, PFS_INVAL, R300_FPI2_OUTA_RCP },
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{ "RSQ", 1, PFS_INVAL, R300_FPI2_OUTA_RSQ },
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{ "EX2", 1, R300_FPI0_OUTC_REPL_ALPHA, R300_FPI2_OUTA_EX2 },
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{ "LG2", 1, R300_FPI0_OUTC_REPL_ALPHA, R300_FPI2_OUTA_LG2 },
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{ "RCP", 1, R300_FPI0_OUTC_REPL_ALPHA, R300_FPI2_OUTA_RCP },
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{ "RSQ", 1, R300_FPI0_OUTC_REPL_ALPHA, R300_FPI2_OUTA_RSQ },
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{ "REPL_ALPHA", 1, R300_FPI0_OUTC_REPL_ALPHA, PFS_INVAL }
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};
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#define MAKE_SWZ3(x, y, z) (MAKE_SWIZZLE4(SWIZZLE_##x, \
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@ -545,12 +547,19 @@ static void emit_arith(struct r300_fragment_program *rp, int op,
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int flags)
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{
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pfs_reg_t src[3] = { src0, src1, src2 };
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int hwdest, hwsrc[3];
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int hwdest, hwsrc;
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int argc;
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int v_idx = rp->v_pos, s_idx = rp->s_pos;
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GLuint inst[4] = { 0, 0, 0, 0 };
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int vop, sop;
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int i;
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#define ARG_NEG (1<<5)
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#define ARG_ABS (1<<6)
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#define ARG_STRIDE 7
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#define SRC_CONST (1<<5)
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#define SRC_STRIDE 6
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if (!dest.valid || !src0.valid || !src1.valid || !src2.valid) {
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ERROR("invalid register. dest/src0/src1/src2 valid = %d/%d/%d/%d\n",
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dest.valid, src0.valid, src1.valid, src2.valid);
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@ -563,34 +572,9 @@ static void emit_arith(struct r300_fragment_program *rp, int op,
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return;
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}
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argc = r300_fpop[op].argc;
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vop = r300_fpop[op].v_op;
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sop = r300_fpop[op].s_op;
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/* grab hwregs of sources */
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for (i=0;i<argc;i++) {
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switch (src[i].type) {
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case REG_TYPE_INPUT:
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hwsrc[i] = rp->inputs[src[i].index];
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rp->used_in_node |= (1 << hwsrc[i]);
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break;
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case REG_TYPE_TEMP:
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/* make sure insn ordering is right... */
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if ((src[i].vcross && v_idx < s_idx) ||
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(src[i].scross && s_idx < v_idx)) {
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sync_streams(rp);
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v_idx = s_idx = rp->v_pos;
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}
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hwsrc[i] = rp->temps[src[i].index];
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rp->used_in_node |= (1 << hwsrc[i]);
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break;
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case REG_TYPE_CONST:
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hwsrc[i] = src[i].index;
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break;
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default:
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ERROR("invalid source reg\n");
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return;
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}
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}
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/* grab hwregs of dest */
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switch (dest.type) {
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case REG_TYPE_TEMP:
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@ -606,42 +590,90 @@ static void emit_arith(struct r300_fragment_program *rp, int op,
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return;
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}
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/* grab hwregs of sources */
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for (i=0;i<3;i++) {
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if (i < argc) {
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inst[0] |= (v_swiz[src[i].v_swz].base + (i * v_swiz[src[i].v_swz].stride)) << (i * 7);
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inst[2] |= (s_swiz[src[i].s_swz].base + (i * s_swiz[src[i].s_swz].stride)) << (i * 7);
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if (src[i].negate) {
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inst[0] |= (1<<5) << (i*7);
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inst[2] |= (1<<5) << (i*7);
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if (i<argc) {
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/* Decide on hardware source index */
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switch (src[i].type) {
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case REG_TYPE_INPUT:
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hwsrc = rp->inputs[src[i].index];
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rp->used_in_node |= (1 << hwsrc);
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inst[1] |= hwsrc << (i * SRC_STRIDE);
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inst[3] |= hwsrc << (i * SRC_STRIDE);
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break;
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case REG_TYPE_TEMP:
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/* make sure insn ordering is right... */
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if ((src[i].vcross && v_idx < s_idx) ||
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(src[i].scross && s_idx < v_idx)) {
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sync_streams(rp);
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v_idx = s_idx = rp->v_pos;
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}
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hwsrc = rp->temps[src[i].index];
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rp->used_in_node |= (1 << hwsrc);
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inst[1] |= hwsrc << (i * SRC_STRIDE);
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inst[3] |= hwsrc << (i * SRC_STRIDE);
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break;
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case REG_TYPE_CONST:
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hwsrc = src[i].index;
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inst[1] |= ((hwsrc | SRC_CONST) << (i * SRC_STRIDE));
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inst[3] |= ((hwsrc | SRC_CONST) << (i * SRC_STRIDE));
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break;
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default:
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ERROR("invalid source reg\n");
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return;
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}
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inst[1] |= hwsrc[i] << (i*6);
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inst[3] |= hwsrc[i] << (i*6);
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if (src[i].type == REG_TYPE_CONST) {
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inst[1] |= (1<<5) << (i*6);
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inst[3] |= (1<<5) << (i*6);
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/* Swizzling/Negation */
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if (vop == R300_FPI0_OUTC_REPL_ALPHA)
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inst[0] |= R300_FPI0_ARGC_ZERO << (i * ARG_STRIDE);
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else
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inst[0] |= (v_swiz[src[i].v_swz].base + (i * v_swiz[src[i].v_swz].stride)) << (i*ARG_STRIDE);
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inst[2] |= (s_swiz[src[i].s_swz].base + (i * s_swiz[src[i].s_swz].stride)) << (i*ARG_STRIDE);
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if (src[i].negate) {
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inst[0] |= ARG_NEG << (i * ARG_STRIDE);
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inst[2] |= ARG_NEG << (i * ARG_STRIDE);
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}
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if (flags & PFS_FLAG_ABS) {
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inst[0] |= ARG_ABS << (i * ARG_STRIDE);
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inst[2] |= ARG_ABS << (i * ARG_STRIDE);
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}
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} else {
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/* read constant zero, may aswell use a ZERO swizzle aswell.. */
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inst[0] |= R300_FPI0_ARGC_ZERO << (i*7);
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inst[2] |= R300_FPI2_ARGA_ZERO << (i*7);
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inst[1] |= (1<<5) << (i*6);
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inst[3] |= (1<<5) << (i*6);
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/* read constant 0, use zero swizzle aswell */
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inst[0] |= R300_FPI0_ARGC_ZERO << (i*ARG_STRIDE);
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inst[1] |= SRC_CONST << (i*SRC_STRIDE);
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inst[2] |= R300_FPI2_ARGA_ZERO << (i*ARG_STRIDE);
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inst[3] |= SRC_CONST << (i*SRC_STRIDE);
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}
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}
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if (flags & PFS_FLAG_SAT) {
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vop |= R300_FPI0_OUTC_SAT;
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sop |= R300_FPI2_OUTA_SAT;
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}
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if (mask & WRITEMASK_XYZ) {
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rp->alu.inst[v_idx].inst0 = inst[0] | r300_fpop[op].v_op | flags;
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if (r300_fpop[op].v_op == R300_FPI0_OUTC_REPL_ALPHA) {
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sync_streams(rp);
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s_idx = v_idx = rp->v_pos;
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}
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rp->alu.inst[v_idx].inst0 = inst[0] | vop;
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rp->alu.inst[v_idx].inst1 = inst[1] |
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(hwdest << R300_FPI1_DSTC_SHIFT) |
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((mask & WRITEMASK_XYZ) << (dest.type == REG_TYPE_OUTPUT ? 26 : 23));
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rp->v_pos = v_idx + 1;
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}
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if (mask & WRITEMASK_W) {
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rp->alu.inst[s_idx].inst2 = inst[2] | r300_fpop[op].s_op | flags;
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if ((mask & WRITEMASK_W) || r300_fpop[op].v_op == R300_FPI0_OUTC_REPL_ALPHA) {
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rp->alu.inst[s_idx].inst2 = inst[2] | sop;
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rp->alu.inst[s_idx].inst3 = inst[3] |
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(hwdest << R300_FPI3_DSTA_SHIFT) |
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(1 << (dest.type == REG_TYPE_OUTPUT ? 24 : 23));
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(((mask & WRITEMASK_W)?1:0) << (dest.type == REG_TYPE_OUTPUT ? 24 : 23));
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rp->s_pos = s_idx + 1;
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}
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@ -663,7 +695,9 @@ static GLboolean parse_program(struct r300_fragment_program *rp)
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}
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for (fpi=mp->Instructions; fpi->Opcode != FP_OPCODE_END; fpi++) {
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if (inst->Saturate) flags = R300_FPI0_OUTC_SAT; /* same for OUTA */
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if (fpi->Saturate) {
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flags = PFS_FLAG_SAT;
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}
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switch (fpi->Opcode) {
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case FP_OPCODE_ABS:
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@ -681,6 +715,20 @@ static GLboolean parse_program(struct r300_fragment_program *rp)
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ERROR("unknown fpi->Opcode %d\n", fpi->Opcode);
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break;
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case FP_OPCODE_DP3:
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dest = t_dst(rp, fpi->DstReg);
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if (fpi->DstReg.WriteMask & WRITEMASK_W) {
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/* I assume these need to share the same alu slot */
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sync_streams(rp);
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emit_arith(rp, PFS_OP_DP4, dest, WRITEMASK_W,
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pfs_zero, pfs_zero, pfs_zero,
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flags);
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}
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emit_arith(rp, PFS_OP_DP3, t_dst(rp, fpi->DstReg),
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fpi->DstReg.WriteMask & WRITEMASK_XYZ,
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t_src(rp, fpi->SrcReg[0]),
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t_src(rp, fpi->SrcReg[1]),
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pfs_zero, flags);
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break;
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case FP_OPCODE_DP4:
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case FP_OPCODE_DPH:
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case FP_OPCODE_DST:
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@ -732,8 +780,31 @@ static GLboolean parse_program(struct r300_fragment_program *rp)
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flags);
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break;
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case FP_OPCODE_POW:
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/* I don't like this, and it's probably wrong in some
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* circumstances... Needs checking */
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src0 = t_src(rp, fpi->SrcReg[0]);
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src1 = t_src(rp, fpi->SrcReg[1]);
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dest = t_dst(rp, fpi->DstReg);
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temp = get_temp_reg(rp);
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temp.s_swz = SWIZZLE_X; /* cheat, bypass swizzle code */
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emit_arith(rp, PFS_OP_LG2, temp, WRITEMASK_X,
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src0, pfs_zero, pfs_zero, 0);
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emit_arith(rp, PFS_OP_MAD, temp, WRITEMASK_X,
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temp, src1, pfs_zero, 0);
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emit_arith(rp, PFS_OP_EX2, dest, fpi->DstReg.WriteMask,
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temp, pfs_zero, pfs_zero, 0);
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free_temp(rp, temp);
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break;
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case FP_OPCODE_RCP:
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ERROR("unknown fpi->Opcode %d\n", fpi->Opcode);
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break;
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case FP_OPCODE_RSQ:
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emit_arith(rp, PFS_OP_RSQ, t_dst(rp, fpi->DstReg),
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fpi->DstReg.WriteMask,
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t_src(rp, fpi->SrcReg[0]), pfs_zero, pfs_zero,
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flags | PFS_FLAG_ABS);
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break;
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case FP_OPCODE_SCS:
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case FP_OPCODE_SGE:
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case FP_OPCODE_SIN:
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@ -873,7 +944,7 @@ void init_program(struct r300_fragment_program *rp)
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void translate_fragment_shader(struct r300_fragment_program *rp)
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{
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int i;
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init_program(rp);
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if (parse_program(rp) == GL_FALSE) {
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@ -39,8 +39,12 @@ typedef struct _pfs_reg_t {
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#define PFS_OP_LG2 8
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#define PFS_OP_RCP 9
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#define PFS_OP_RSQ 10
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#define MAX_PFS_OP 10
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#define PFS_OP_REPL_ALPHA 11
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#define MAX_PFS_OP 11
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#define OP(n) PFS_OP_##n
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#define PFS_FLAG_SAT (1 << 0)
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#define PFS_FLAG_ABS (1 << 1)
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#endif
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@ -1000,12 +1000,15 @@ I am fairly certain that they are correct unless stated otherwise in comments.
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# define R300_FPI2_ARG0A_SHIFT 0
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# define R300_FPI2_ARG0A_MASK (31 << 0)
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# define R300_FPI2_ARG0A_NEG (1 << 5)
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# define R300_FPI2_ARG0A_ABS (1 << 6) /* GUESS */
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# define R300_FPI2_ARG1A_SHIFT 7
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# define R300_FPI2_ARG1A_MASK (31 << 7)
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# define R300_FPI2_ARG1A_NEG (1 << 12)
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# define R300_FPI2_ARG1A_ABS (1 << 13) /* GUESS */
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# define R300_FPI2_ARG2A_SHIFT 14
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# define R300_FPI2_ARG2A_MASK (31 << 14)
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# define R300_FPI2_ARG2A_NEG (1 << 19)
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# define R300_FPI2_ARG2A_ABS (1 << 20) /* GUESS */
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# define R300_FPI2_SPECIAL_LRP (1 << 21)
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# define R300_FPI2_OUTA_MAD (0 << 23)
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# define R300_FPI2_OUTA_DP4 (1 << 23)
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