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radv/amdgpu: Use STACK_ARRAY for IB array to reduce stack usage.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22668>
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1 changed files with 8 additions and 5 deletions
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@ -909,10 +909,17 @@ radv_amdgpu_winsys_cs_submit_internal(
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struct radv_amdgpu_cs *last_cs = radv_amdgpu_cs(cs_array[cs_count - 1]);
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struct radv_amdgpu_cs *last_cs = radv_amdgpu_cs(cs_array[cs_count - 1]);
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struct radv_amdgpu_winsys *ws = last_cs->ws;
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struct radv_amdgpu_winsys *ws = last_cs->ws;
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assert(cs_count);
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const unsigned num_pre_post_cs =
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MAX2(initial_preamble_count, continue_preamble_count) + postamble_count;
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const unsigned ib_array_size = MIN2(RADV_MAX_IBS_PER_SUBMIT, num_pre_post_cs + cs_count);
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STACK_ARRAY(struct radv_amdgpu_cs_ib_info, ibs, ib_array_size);
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struct drm_amdgpu_bo_list_entry *handles = NULL;
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struct drm_amdgpu_bo_list_entry *handles = NULL;
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unsigned num_handles = 0;
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unsigned num_handles = 0;
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u_rwlock_rdlock(&ws->global_bo_list.lock);
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u_rwlock_rdlock(&ws->global_bo_list.lock);
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result = radv_amdgpu_get_bo_list(
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result = radv_amdgpu_get_bo_list(
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ws, &cs_array[0], cs_count, initial_preamble_cs, initial_preamble_count, continue_preamble_cs,
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ws, &cs_array[0], cs_count, initial_preamble_cs, initial_preamble_count, continue_preamble_cs,
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continue_preamble_count, postamble_cs, postamble_count, &num_handles, &handles);
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continue_preamble_count, postamble_cs, postamble_count, &num_handles, &handles);
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@ -921,7 +928,6 @@ radv_amdgpu_winsys_cs_submit_internal(
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/* Configure the CS request. */
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/* Configure the CS request. */
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const uint8_t *max_ib_per_ip = ws->info.max_submitted_ibs;
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const uint8_t *max_ib_per_ip = ws->info.max_submitted_ibs;
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struct radv_amdgpu_cs_ib_info ibs[RADV_MAX_IBS_PER_SUBMIT];
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struct radv_amdgpu_cs_request request = {
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struct radv_amdgpu_cs_request request = {
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.ip_type = last_cs->hw_ip,
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.ip_type = last_cs->hw_ip,
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.ip_instance = 0,
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.ip_instance = 0,
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@ -932,10 +938,6 @@ radv_amdgpu_winsys_cs_submit_internal(
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.number_of_ibs = 0, /* set below */
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.number_of_ibs = 0, /* set below */
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};
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};
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assert(cs_count);
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assert(MAX2(initial_preamble_count, continue_preamble_count) + postamble_count <
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RADV_MAX_IBS_PER_SUBMIT);
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for (unsigned cs_idx = 0, cs_ib_idx = 0; cs_idx < cs_count;) {
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for (unsigned cs_idx = 0, cs_ib_idx = 0; cs_idx < cs_count;) {
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struct radeon_cmdbuf **preambles = cs_idx ? continue_preamble_cs : initial_preamble_cs;
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struct radeon_cmdbuf **preambles = cs_idx ? continue_preamble_cs : initial_preamble_cs;
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const unsigned preamble_count = cs_idx ? continue_preamble_count : initial_preamble_count;
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const unsigned preamble_count = cs_idx ? continue_preamble_count : initial_preamble_count;
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@ -1029,6 +1031,7 @@ radv_amdgpu_winsys_cs_submit_internal(
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fail:
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fail:
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u_rwlock_rdunlock(&ws->global_bo_list.lock);
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u_rwlock_rdunlock(&ws->global_bo_list.lock);
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STACK_ARRAY_FINISH(ibs);
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return result;
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return result;
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}
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}
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