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i965: Move 3-src subnr swizzle handling into the vec4 backend.
While most align16 instructions only support a SubRegNum of 0 or 4 (using swizzling to control the other channels), 3-src instructions actually support arbitrary SubRegNums. When the RepCtrl bit is set, we believe it ignores the swizzle and uses the equivalent of a <0,1,0> region from the subnr. In the past, we adopted a vec4-centric approach of specifying subnr of 0 or 4 and a swizzle, then having brw_eu_emit.c convert that to a proper SubRegNum. This isn't a great fit for the scalar backend, where we don't set swizzles at all, and happily set subnrs in the range [0, 7]. This patch changes brw_eu_emit.c to use subnr and swizzle directly, relying on the higher levels to set them sensibly. This should fix problems where scalar sources get copy propagated into 3-src instructions in the FS backend. I've only observed this with TES push model inputs, but I suppose it could happen in other cases. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
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2 changed files with 18 additions and 6 deletions
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@ -847,12 +847,11 @@ brw_alu2(struct brw_codegen *p, unsigned opcode,
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static int
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get_3src_subreg_nr(struct brw_reg reg)
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{
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if (reg.vstride == BRW_VERTICAL_STRIDE_0) {
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assert(brw_is_single_value_swizzle(reg.swizzle));
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return reg.subnr / 4 + BRW_GET_SWZ(reg.swizzle, 0);
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} else {
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return reg.subnr / 4;
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}
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/* Normally, SubRegNum is in bytes (0..31). However, 3-src instructions
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* use 32-bit units (components 0..7). Since they only support F/D/UD
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* types, this doesn't lose any flexibility, but uses fewer bits.
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*/
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return reg.subnr / 4;
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}
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static brw_inst *
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@ -1784,9 +1784,22 @@ vec4_visitor::convert_to_hw_regs()
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case ATTR:
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unreachable("not reached");
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}
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src = reg;
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}
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if (inst->is_3src()) {
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/* 3-src instructions with scalar sources support arbitrary subnr,
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* but don't actually use swizzles. Convert swizzle into subnr.
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*/
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for (int i = 0; i < 3; i++) {
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if (inst->src[i].vstride == BRW_VERTICAL_STRIDE_0) {
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assert(brw_is_single_value_swizzle(inst->src[i].swizzle));
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inst->src[i].subnr += 4 * BRW_GET_SWZ(inst->src[i].swizzle, 0);
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}
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}
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}
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dst_reg &dst = inst->dst;
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struct brw_reg reg;
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