diff --git a/src/amd/vulkan/meta/radv_meta_decompress.c b/src/amd/vulkan/meta/radv_meta_decompress.c index 51ed89f62df..4d4b4ee55a2 100644 --- a/src/amd/vulkan/meta/radv_meta_decompress.c +++ b/src/amd/vulkan/meta/radv_meta_decompress.c @@ -456,6 +456,7 @@ radv_expand_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image if (cmd_buffer->qf == RADV_QUEUE_GENERAL) { radv_process_depth_stencil(cmd_buffer, image, subresourceRange, sample_locs); } else { + assert(cmd_buffer->qf == RADV_QUEUE_COMPUTE); radv_expand_depth_stencil_compute(cmd_buffer, image, subresourceRange); } } diff --git a/src/amd/vulkan/meta/radv_meta_fast_clear.c b/src/amd/vulkan/meta/radv_meta_fast_clear.c index 3200f652e5d..7fb26cd3b9d 100644 --- a/src/amd/vulkan/meta/radv_meta_fast_clear.c +++ b/src/amd/vulkan/meta/radv_meta_fast_clear.c @@ -557,8 +557,10 @@ radv_decompress_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image barrier.layout_transitions.dcc_decompress = 1; radv_describe_layout_transition(cmd_buffer, &barrier); - if (cmd_buffer->qf == RADV_QUEUE_GENERAL) + if (cmd_buffer->qf == RADV_QUEUE_GENERAL) { radv_process_color_image(cmd_buffer, image, subresourceRange, DCC_DECOMPRESS); - else + } else { + assert(cmd_buffer->qf == RADV_QUEUE_COMPUTE); radv_decompress_dcc_compute(cmd_buffer, image, subresourceRange); + } } diff --git a/src/amd/vulkan/meta/radv_meta_fmask_expand.c b/src/amd/vulkan/meta/radv_meta_fmask_expand.c index 46321e26645..db427a6b2ab 100644 --- a/src/amd/vulkan/meta/radv_meta_fmask_expand.c +++ b/src/amd/vulkan/meta/radv_meta_fmask_expand.c @@ -105,6 +105,8 @@ radv_process_color_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image * VkPipeline pipeline; VkResult result; + assert(cmd_buffer->qf == RADV_QUEUE_GENERAL || cmd_buffer->qf == RADV_QUEUE_COMPUTE); + result = get_pipeline(device, samples_log2, &pipeline, &layout); if (result != VK_SUCCESS) { vk_command_buffer_set_error(&cmd_buffer->vk, result);