diff --git a/src/gallium/drivers/iris/iris_bufmgr.h b/src/gallium/drivers/iris/iris_bufmgr.h
index 77e8fd9aab6..89a2e993aab 100644
--- a/src/gallium/drivers/iris/iris_bufmgr.h
+++ b/src/gallium/drivers/iris/iris_bufmgr.h
@@ -113,6 +113,8 @@ enum iris_domain {
    IRIS_DOMAIN_VF_READ,
    /** Texture cache. */
    IRIS_DOMAIN_SAMPLER_READ,
+   /** Pull-style shader constant loads. */
+   IRIS_DOMAIN_PULL_CONSTANT_READ,
    /** Any other read-only cache. */
    IRIS_DOMAIN_OTHER_READ,
    /** Number of caching domains. */
diff --git a/src/gallium/drivers/iris/iris_pipe_control.c b/src/gallium/drivers/iris/iris_pipe_control.c
index a9b2bc538ff..e9ed766e26e 100644
--- a/src/gallium/drivers/iris/iris_pipe_control.c
+++ b/src/gallium/drivers/iris/iris_pipe_control.c
@@ -184,6 +184,8 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch,
                              struct iris_bo *bo,
                              enum iris_domain access)
 {
+   const struct brw_compiler *compiler = batch->screen->compiler;
+
    const uint32_t all_flush_bits = (PIPE_CONTROL_CACHE_FLUSH_BITS |
                                     PIPE_CONTROL_STALL_AT_SCOREBOARD |
                                     PIPE_CONTROL_FLUSH_ENABLE);
@@ -194,6 +196,7 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch,
       [IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE,
       [IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,
       [IRIS_DOMAIN_SAMPLER_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,
+      [IRIS_DOMAIN_PULL_CONSTANT_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,
       [IRIS_DOMAIN_OTHER_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,
    };
    const uint32_t invalidate_bits[NUM_IRIS_DOMAINS] = {
@@ -203,7 +206,10 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch,
       [IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE,
       [IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_VF_CACHE_INVALIDATE,
       [IRIS_DOMAIN_SAMPLER_READ] = PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE,
-      [IRIS_DOMAIN_OTHER_READ] = PIPE_CONTROL_CONST_CACHE_INVALIDATE,
+      [IRIS_DOMAIN_PULL_CONSTANT_READ] = PIPE_CONTROL_CONST_CACHE_INVALIDATE |
+         (compiler->indirect_ubos_use_sampler ?
+          PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE :
+          PIPE_CONTROL_DATA_CACHE_FLUSH),
    };
    uint32_t bits = 0;
 
diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c
index 9296db3bffb..f4ecd1b9774 100644
--- a/src/gallium/drivers/iris/iris_resolve.c
+++ b/src/gallium/drivers/iris/iris_resolve.c
@@ -381,7 +381,7 @@ flush_ubos(struct iris_batch *batch,
       const int i = u_bit_scan(&cbufs);
       struct pipe_shader_buffer *cbuf = &shs->constbuf[i];
       struct iris_resource *res = (void *)cbuf->buffer;
-      iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_OTHER_READ);
+      iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_PULL_CONSTANT_READ);
    }
 
    shs->dirty_cbufs = 0;
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 63a3d44b5fb..4f04e3928d9 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -5094,7 +5094,7 @@ iris_populate_binding_table(struct iris_context *ice,
       struct iris_state_ref *grid_data = &ice->state.grid_size;
       struct iris_state_ref *grid_state = &ice->state.grid_surf_state;
       iris_use_pinned_bo(batch, iris_resource_bo(grid_data->res), false,
-                         IRIS_DOMAIN_OTHER_READ);
+                         IRIS_DOMAIN_PULL_CONSTANT_READ);
       iris_use_pinned_bo(batch, iris_resource_bo(grid_state->res), false,
                          IRIS_DOMAIN_NONE);
       push_bt_entry(grid_state->offset);
@@ -5153,7 +5153,7 @@ iris_populate_binding_table(struct iris_context *ice,
    foreach_surface_used(i, IRIS_SURFACE_GROUP_UBO) {
       uint32_t addr = use_ubo_ssbo(batch, ice, &shs->constbuf[i],
                                    &shs->constbuf_surf_state[i], false,
-                                   IRIS_DOMAIN_OTHER_READ);
+                                   IRIS_DOMAIN_PULL_CONSTANT_READ);
       push_bt_entry(addr);
    }
 
@@ -7611,6 +7611,7 @@ batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags)
                     PIPE_CONTROL_STALL_AT_SCOREBOARD))) {
          iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_VF_READ);
          iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_SAMPLER_READ);
+         iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_PULL_CONSTANT_READ);
          iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_OTHER_READ);
       }
    }
@@ -7633,8 +7634,24 @@ batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags)
    if ((flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE))
       iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_SAMPLER_READ);
 
+   /* Technically, to invalidate IRIS_DOMAIN_PULL_CONSTANT_READ, we need
+    * both "Constant Cache Invalidate" and either "Texture Cache Invalidate"
+    * or "Data Cache Flush" set, depending on the setting of
+    * compiler->indirect_ubos_use_sampler.
+    *
+    * However, "Data Cache Flush" and "Constant Cache Invalidate" will never
+    * appear in the same PIPE_CONTROL command, because one is bottom-of-pipe
+    * while the other is top-of-pipe.  Because we only look at one flush at
+    * a time, we won't see both together.
+    *
+    * To deal with this, we mark it as invalidated when the constant cache
+    * is invalidated, and trust the callers to also flush the other related
+    * cache correctly at the same time.
+    */
    if ((flags & PIPE_CONTROL_CONST_CACHE_INVALIDATE))
-      iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_OTHER_READ);
+      iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_PULL_CONSTANT_READ);
+
+   /* IRIS_DOMAIN_OTHER_READ no longer uses any caches. */
 }
 
 static unsigned