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amd/common: add GFX10 chips
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
parent
677bb80c98
commit
536782b0b7
5 changed files with 28 additions and 5 deletions
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@ -94,7 +94,9 @@
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#define AMDGPU_RAVEN_RANGE 0x01, 0x81
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#define AMDGPU_RAVEN2_RANGE 0x81, 0xFF
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#define AMDGPU_NAVI10_RANGE 0x01, 0xFF
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#define AMDGPU_NAVI10_RANGE 0x01, 0x0A
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#define AMDGPU_NAVI12_RANGE 0x0A, 0x14
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#define AMDGPU_NAVI14_RANGE 0x14, 0x28
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#define AMDGPU_EXPAND_FIX(x) x
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#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
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@ -139,5 +141,7 @@
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#define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2)
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#define ASICREV_IS_NAVI10_P(r) ASICREV_IS(r, NAVI10)
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#define ASICREV_IS_NAVI12(r) ASICREV_IS(r, NAVI12)
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#define ASICREV_IS_NAVI14(r) ASICREV_IS(r, NAVI14)
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#endif // _AMDGPU_ASIC_ADDR_H
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@ -323,7 +323,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
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info->name = "RAVEN2";
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}
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if (info->family >= CHIP_VEGA10)
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if (info->family >= CHIP_NAVI10)
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info->chip_class = GFX10;
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else if (info->family >= CHIP_VEGA10)
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info->chip_class = GFX9;
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else if (info->family >= CHIP_TONGA)
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info->chip_class = GFX8;
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@ -413,7 +415,11 @@ bool ac_query_gpu_info(int fd, void *dev_p,
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fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
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info->clock_crystal_freq = 1;
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}
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info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
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if (info->chip_class >= GFX10) {
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info->tcc_cache_line_size = 128;
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} else {
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info->tcc_cache_line_size = 64;
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}
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info->gb_addr_config = amdinfo->gb_addr_cfg;
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if (info->chip_class == GFX9) {
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info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
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@ -133,6 +133,12 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
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return "gfx906";
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case CHIP_RAVEN2:
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return HAVE_LLVM >= 0x0800 ? "gfx909" : "gfx902";
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case CHIP_NAVI10:
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return "gfx1010";
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case CHIP_NAVI12:
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return "gfx1011";
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case CHIP_NAVI14:
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return "gfx1012";
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default:
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return "";
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}
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@ -149,8 +155,9 @@ static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
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LLVMTargetRef target = ac_get_llvm_target(triple);
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snprintf(features, sizeof(features),
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"+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s%s",
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"+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s%s%s",
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HAVE_LLVM >= 0x0800 ? "" : ",+vgpr-spilling",
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family >= CHIP_NAVI10 ? ",+wavefrontsize64,-wavefrontsize32" : "",
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tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
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tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
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tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
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@ -97,6 +97,9 @@ enum radeon_family {
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CHIP_VEGA20,
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CHIP_RAVEN,
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CHIP_RAVEN2,
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CHIP_NAVI10,
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CHIP_NAVI12,
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CHIP_NAVI14,
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CHIP_LAST,
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};
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@ -113,6 +116,7 @@ enum chip_class {
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GFX7,
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GFX8,
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GFX9,
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GFX10,
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};
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#endif
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@ -65,7 +65,9 @@ static void handle_env_var_force_family(struct amdgpu_winsys *ws)
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ws->info.family = i;
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ws->info.name = "GCN-NOOP";
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if (i >= CHIP_VEGA10)
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if (i >= CHIP_NAVI10)
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ws->info.chip_class = GFX10;
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else if (i >= CHIP_VEGA10)
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ws->info.chip_class = GFX9;
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else if (i >= CHIP_TONGA)
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ws->info.chip_class = GFX8;
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