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i965: Add chipset limits for Haswell GT1/GT2.

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The maximum number of URB entries come from the 3DSTATE_URB_VS and
3DSTATE_URB_GS state packet documentation; the thread count information
comes from the 3DSTATE_VS and 3DSTATE_PS state packet documentation.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
(cherry picked from commit 9add4e8038)
This commit is contained in:
Kenneth Graunke 2011-08-12 18:27:16 -07:00
parent a7e2c615f1
commit 535e95299a
1 changed files with 17 additions and 1 deletions
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18
src/mesa/drivers/dri/i965/brw_context.c
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@ -278,7 +278,23 @@ brwCreateContext(int api,
}
/* WM maximum threads is number of EUs times number of threads per EU. */
if (intel->gen >= 7) {
assert(intel->gen <= 7);
if (intel->is_haswell) {
if (intel->gt == 1) {
brw->max_wm_threads = 102;
brw->max_vs_threads = 70;
brw->urb.size = 128;
brw->urb.max_vs_entries = 640;
brw->urb.max_gs_entries = 256;
} else if (intel->gt == 2) {
brw->max_wm_threads = 204;
brw->max_vs_threads = 280;
brw->urb.size = 256;
brw->urb.max_vs_entries = 1664;
brw->urb.max_gs_entries = 640;
}
} else if (intel->gen == 7) {
if (intel->gt == 1) {
brw->max_wm_threads = 48;
brw->max_vs_threads = 36;