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r600g: don't use register mask for SQ_GPR_RESOURCE_MGMT_1

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Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák 2012-01-28 04:25:31 +01:00
parent 177845daa1
commit 5345e3ea86
2 changed files with 4 additions and 1 deletions
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1
src/gallium/drivers/r600/r600_pipe.h
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@ -188,6 +188,7 @@ struct r600_pipe_context {
struct blitter_context *blitter;
enum radeon_family family;
enum chip_class chip_class;
unsigned r6xx_num_clause_temp_gprs;
void *custom_dsa_flush;
struct r600_screen *screen;
struct radeon_winsys *ws;

4
src/gallium/drivers/r600/r600_state.c
View file

@ -1829,8 +1829,9 @@ void r600_adjust_gprs(struct r600_pipe_context *rctx)
tmp = 0;
tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
rstate.nregs = 0;
r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0x0FFFFFFF, NULL, 0);
r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
r600_context_pipe_state_set(&rctx->ctx, &rstate);
}
@ -2008,6 +2009,7 @@ void r600_init_config(struct r600_pipe_context *rctx)
tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
/* SQ_GPR_RESOURCE_MGMT_2 */