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synced 2026-05-05 07:28:11 +02:00
freedreno/a6xx: Switch to relying on fd6_view for our texture descriptors.
Having checked the deltas between fdl6_view and what we did before, switch over to fdl6_view now. No statistically significant difference on no-hw drawoverhead 8-texture change (n=50) with the texture cache disabled from this and the previous commit. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13443>
This commit is contained in:
Emma Anholt
Marge Bot
parent
84377785a4
commit
533e486923
3 changed files with 20 additions and 157 deletions
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@ -393,35 +393,35 @@ fd6_emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
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view = &dummy_view;
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}
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OUT_RING(state, view->texconst0);
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OUT_RING(state, view->texconst1);
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OUT_RING(state, view->texconst2);
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OUT_RING(state, view->texconst3);
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OUT_RING(state, view->descriptor[0]);
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OUT_RING(state, view->descriptor[1]);
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OUT_RING(state, view->descriptor[2]);
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OUT_RING(state, view->descriptor[3]);
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if (view->ptr1) {
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OUT_RELOC(state, view->ptr1->bo, view->offset1,
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(uint64_t)view->texconst5 << 32, 0);
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OUT_RELOC(state, view->ptr1->bo, view->descriptor[4],
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(uint64_t)view->descriptor[5] << 32, 0);
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} else {
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OUT_RING(state, 0x00000000);
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OUT_RING(state, view->texconst5);
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OUT_RING(state, view->descriptor[4]);
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OUT_RING(state, view->descriptor[5]);
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}
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OUT_RING(state, view->texconst6);
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OUT_RING(state, view->descriptor[6]);
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if (view->ptr2) {
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OUT_RELOC(state, view->ptr2->bo, view->offset2, 0, 0);
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OUT_RELOC(state, view->ptr2->bo, view->descriptor[7], 0, 0);
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} else {
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OUT_RING(state, 0);
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OUT_RING(state, 0);
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OUT_RING(state, view->descriptor[7]);
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OUT_RING(state, view->descriptor[8]);
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}
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OUT_RING(state, view->texconst9);
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OUT_RING(state, view->texconst10);
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OUT_RING(state, view->texconst11);
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OUT_RING(state, 0);
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OUT_RING(state, 0);
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OUT_RING(state, 0);
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OUT_RING(state, 0);
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OUT_RING(state, view->descriptor[9]);
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OUT_RING(state, view->descriptor[10]);
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OUT_RING(state, view->descriptor[11]);
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OUT_RING(state, view->descriptor[12]);
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OUT_RING(state, view->descriptor[13]);
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OUT_RING(state, view->descriptor[14]);
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OUT_RING(state, view->descriptor[15]);
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}
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if (v) {
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@ -213,8 +213,6 @@ fd6_sampler_view_update(struct fd_context *ctx,
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struct pipe_resource *prsc = cso->texture;
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struct fd_resource *rsc = fd_resource(prsc);
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enum pipe_format format = cso->format;
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bool ubwc_enabled = false;
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unsigned lvl, layers = 0;
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fd6_validate_format(ctx, rsc, cso->format);
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@ -236,14 +234,6 @@ fd6_sampler_view_update(struct fd_context *ctx,
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fdl6_buffer_view_init(so->descriptor, cso->format, swiz, iova,
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cso->u.buf.size);
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unsigned elements = cso->u.buf.size / util_format_get_blocksize(format);
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lvl = 0;
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so->texconst1 = A6XX_TEX_CONST_1_WIDTH(elements & MASK(15)) |
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A6XX_TEX_CONST_1_HEIGHT(elements >> 15);
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so->texconst2 = A6XX_TEX_CONST_2_UNK4 | A6XX_TEX_CONST_2_UNK31;
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so->offset1 = cso->u.buf.offset;
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} else {
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struct fdl_view_args args = {
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/* Using relocs for addresses still */
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@ -278,141 +268,17 @@ fd6_sampler_view_update(struct fd_context *ctx,
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ctx->screen->info->a6xx.has_z24uint_s8uint);
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memcpy(so->descriptor, view.descriptor, sizeof(so->descriptor));
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unsigned miplevels;
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lvl = fd_sampler_first_level(cso);
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miplevels = fd_sampler_last_level(cso) - lvl;
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layers = cso->u.tex.last_layer - cso->u.tex.first_layer + 1;
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so->texconst0 |= A6XX_TEX_CONST_0_MIPLVLS(miplevels);
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so->texconst1 = A6XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) |
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A6XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));
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so->texconst2 = A6XX_TEX_CONST_2_PITCHALIGN(rsc->layout.pitchalign - 6) |
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A6XX_TEX_CONST_2_PITCH(fd_resource_pitch(rsc, lvl));
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ubwc_enabled = fd_resource_ubwc_enabled(rsc, lvl);
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if (rsc->b.b.format == PIPE_FORMAT_R8_G8B8_420_UNORM) {
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/* In case of biplanar R8_G8B8, the UBWC metadata address in
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* dwords 7 and 8, is instead the pointer to the second plane.
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*/
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so->ptr2 = plane1;
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so->texconst6 =
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A6XX_TEX_CONST_6_PLANE_PITCH(fd_resource_pitch(plane1, lvl));
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if (ubwc_enabled) {
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/* Further, if using UBWC with R8_G8B8, we only point to the
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* UBWC header and the color data is expected to follow immediately.
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*/
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so->offset1 =
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fd_resource_ubwc_offset(rsc, lvl, cso->u.tex.first_layer);
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so->offset2 =
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fd_resource_ubwc_offset(plane1, lvl, cso->u.tex.first_layer);
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} else {
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so->offset1 = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer);
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so->offset2 =
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fd_resource_offset(plane1, lvl, cso->u.tex.first_layer);
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}
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} else {
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so->offset1 = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer);
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if (ubwc_enabled) {
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if (fd_resource_ubwc_enabled(rsc, fd_sampler_first_level(cso))) {
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so->ptr2 = rsc;
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so->offset2 =
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fd_resource_ubwc_offset(rsc, lvl, cso->u.tex.first_layer);
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}
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}
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}
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so->texconst0 |=
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fd6_tex_const_0(prsc, lvl, cso->format, cso->swizzle_r, cso->swizzle_g,
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cso->swizzle_b, cso->swizzle_a);
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so->texconst2 |= A6XX_TEX_CONST_2_TYPE(fd6_tex_type(cso->target));
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switch (cso->target) {
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case PIPE_TEXTURE_RECT:
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case PIPE_TEXTURE_1D:
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case PIPE_TEXTURE_2D:
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so->texconst3 = A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
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so->texconst5 = A6XX_TEX_CONST_5_DEPTH(1);
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break;
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case PIPE_TEXTURE_1D_ARRAY:
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case PIPE_TEXTURE_2D_ARRAY:
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so->texconst3 = A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
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so->texconst5 = A6XX_TEX_CONST_5_DEPTH(layers);
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break;
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case PIPE_TEXTURE_CUBE:
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case PIPE_TEXTURE_CUBE_ARRAY:
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so->texconst3 = A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
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so->texconst5 = A6XX_TEX_CONST_5_DEPTH(layers / 6);
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break;
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case PIPE_TEXTURE_3D:
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so->texconst3 =
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A6XX_TEX_CONST_3_MIN_LAYERSZ(
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fd_resource_slice(rsc, prsc->last_level)->size0) |
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A6XX_TEX_CONST_3_ARRAY_PITCH(fd_resource_slice(rsc, lvl)->size0);
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so->texconst5 = A6XX_TEX_CONST_5_DEPTH(u_minify(prsc->depth0, lvl));
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break;
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default:
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break;
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}
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if (rsc->layout.tile_all)
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so->texconst3 |= A6XX_TEX_CONST_3_TILE_ALL;
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if (ubwc_enabled) {
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uint32_t block_width, block_height;
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fdl6_get_ubwc_blockwidth(&rsc->layout, &block_width, &block_height);
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so->texconst3 |= A6XX_TEX_CONST_3_FLAG;
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so->texconst9 |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(
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rsc->layout.ubwc_layer_size >> 2);
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so->texconst10 |=
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A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(
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fdl_ubwc_pitch(&rsc->layout, lvl)) |
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A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(util_logbase2_ceil(
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DIV_ROUND_UP(u_minify(prsc->width0, lvl), block_width))) |
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A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(util_logbase2_ceil(
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DIV_ROUND_UP(u_minify(prsc->height0, lvl), block_height)));
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}
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const uint32_t swiz_mask =
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(A6XX_TEX_CONST_0_SWIZ_X__MASK | A6XX_TEX_CONST_0_SWIZ_Y__MASK |
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A6XX_TEX_CONST_0_SWIZ_Z__MASK | A6XX_TEX_CONST_0_SWIZ_W__MASK);
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/* Sanity check that fdl6_view_init matched previous behavior. */
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uint32_t so_descriptor[16] = {
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/* fd6_view applies format swizzles more, and that's fine. */
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so->texconst0 & ~swiz_mask,
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so->texconst1,
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so->texconst2,
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so->texconst3,
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so->offset1,
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so->texconst5,
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so->texconst6,
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so->offset2,
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0,
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so->texconst9,
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so->texconst10,
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so->texconst11,
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};
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bool diff = false;
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for (int i = 0; i < ARRAY_SIZE(so_descriptor); i++) {
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int view_desc = so->descriptor[i];
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if (i == 0)
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view_desc &= ~swiz_mask;
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if (so_descriptor[i] != view_desc) {
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if (!diff) {
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char view_desc[500] = {0};
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debug_describe_sampler_view(view_desc, cso);
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mesa_loge("view mismatch for %s:", view_desc);
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diff = true;
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}
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mesa_loge("TEXCONST[%d] = 0x%08x vs 0x%08x", i, so_descriptor[i],
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view_desc);
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}
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}
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assert(!diff);
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}
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/* NOTE this can be called in either driver thread or frontend thread
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@ -51,9 +51,6 @@ fd6_sampler_stateobj(struct pipe_sampler_state *samp)
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struct fd6_pipe_sampler_view {
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struct pipe_sampler_view base;
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uint32_t texconst0, texconst1, texconst2, texconst3, texconst5;
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uint32_t texconst6, texconst7, texconst8, texconst9, texconst10, texconst11;
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uint32_t offset1, offset2;
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struct fd_resource *ptr1, *ptr2;
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uint16_t seqno;
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