From 53383fe8a55510fa238c17e2bc8a3b4677f5dd36 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Mon, 5 Jun 2023 12:01:19 +0100 Subject: [PATCH] aco: fix ds_sub_gs_reg_rtn validation Signed-off-by: Rhys Perry Reviewed-by: Qiang Yu Fixes: 8d5cc23c186 ("aco: use gds reg when ordered xfb counter add") Part-of: --- src/amd/compiler/aco_validate.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp index 5e2ff297405..e32747b8152 100644 --- a/src/amd/compiler/aco_validate.cpp +++ b/src/amd/compiler/aco_validate.cpp @@ -280,6 +280,7 @@ validate_ir(Program* program) (flat && i == 1) || (instr->isMIMG() && (i == 1 || i == 2)) || ((instr->isMUBUF() || instr->isMTBUF()) && i == 1) || (instr->isScratch() && i == 0) || + (instr->isDS() && i == 0) || (instr->opcode == aco_opcode::p_init_scratch && i == 0); check(can_be_undef, "Undefs can only be used in certain operands", instr.get()); } else { @@ -744,7 +745,8 @@ validate_ir(Program* program) } case Format::DS: { for (const Operand& op : instr->operands) { - check((op.isTemp() && op.regClass().type() == RegType::vgpr) || op.physReg() == m0, + check((op.isTemp() && op.regClass().type() == RegType::vgpr) || op.physReg() == m0 || + op.isUndefined(), "Only VGPRs are valid DS instruction operands", instr.get()); } if (!instr->definitions.empty())