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broadcom/vc5: Add appropriate height padding for bank conflicts.
I thought I didn't need this because I was doing level-0-always-UIF and that the pad there would propagate down, but it turns out that for level 1 the padding ends up being chosen by the HW. This brings us closer to being able to turn on UIF XOR for increased performance, as well.
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4 changed files with 63 additions and 0 deletions
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@ -327,6 +327,52 @@ vc5_resource_get_handle(struct pipe_screen *pscreen,
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return FALSE;
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}
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/**
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* Computes the HW's UIFblock padding for a given height/cpp.
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*
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* The goal of the padding is to keep pages of the same color (bank number) at
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* least half a page away from each other vertically when crossing between
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* between columns of UIF blocks.
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*/
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static uint32_t
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vc5_get_ub_pad(struct vc5_resource *rsc, uint32_t height)
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{
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uint32_t utile_h = vc5_utile_height(rsc->cpp);
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uint32_t uif_block_h = utile_h * 2;
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uint32_t height_ub = height / uif_block_h;
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uint32_t ub_row_size = 256 * 4;
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uint32_t page_ub_rows = VC5_UIFCFG_PAGE_SIZE / ub_row_size;
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uint32_t pc_ub_rows = VC5_PAGE_CACHE_SIZE / ub_row_size;
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uint32_t height_offset_in_pc = height_ub % pc_ub_rows;
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/* For the perfectly-aligned-for-UIF-XOR case, don't add any pad. */
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if (height_offset_in_pc == 0)
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return 0;
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uint32_t half_page_ub_rows = (page_ub_rows * 3) >> 1;
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/* Try padding up to where we're offset by at least half a page. */
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if (height_offset_in_pc < half_page_ub_rows) {
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/* If we fit entirely in the page cache, don't pad. */
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if (height_ub < pc_ub_rows)
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return 0;
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else
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return half_page_ub_rows - height_offset_in_pc;
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}
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/* If we're close to being aligned to page cache size, then round up
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* and rely on XOR.
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*/
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if (height_offset_in_pc > (pc_ub_rows - half_page_ub_rows))
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return pc_ub_rows - height_offset_in_pc;
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/* Otherwise, we're far enough away (top and bottom) to not need any
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* padding.
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*/
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return 0;
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}
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static void
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vc5_setup_slices(struct vc5_resource *rsc)
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{
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@ -400,6 +446,10 @@ vc5_setup_slices(struct vc5_resource *rsc)
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4 * uif_block_w);
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level_height = align(level_height,
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uif_block_h);
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slice->ub_pad = vc5_get_ub_pad(rsc,
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level_height);
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level_height += slice->ub_pad * uif_block_h;
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}
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}
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@ -74,6 +74,7 @@ struct vc5_resource_slice {
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uint32_t offset;
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uint32_t stride;
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uint32_t size;
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uint8_t ub_pad;
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enum vc5_tiling_mode tiling;
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};
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@ -40,6 +40,14 @@ struct vc5_bo;
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#define VC5_MAX_DRAW_BUFFERS 4
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#define VC5_MAX_ATTRIBUTES 16
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/* These are tunable parameters in the HW design, but all the V3D
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* implementations agree.
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*/
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#define VC5_UIFCFG_BANKS 8
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#define VC5_UIFCFG_PAGE_SIZE 4096
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#define VC5_UIFCFG_XOR_VALUE (1 << 4)
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#define VC5_PAGE_CACHE_SIZE (VC5_UIFCFG_PAGE_SIZE * VC5_UIFCFG_BANKS)
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struct vc5_simulator_file;
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struct vc5_screen {
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@ -31,6 +31,7 @@
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#include "util/u_helpers.h"
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#include "vc5_context.h"
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#include "vc5_tiling.h"
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#include "broadcom/common/v3d_macros.h"
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#include "broadcom/cle/v3dx_pack.h"
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@ -787,6 +788,9 @@ vc5_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
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tex.level_0_xor_enable = (rsc->slices[0].tiling ==
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VC5_TILING_UIF_XOR);
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if (tex.level_0_is_strictly_uif)
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tex.level_0_ub_pad = rsc->slices[0].ub_pad;
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#if V3D_VERSION >= 40
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if (tex.uif_xor_disable ||
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tex.level_0_is_strictly_uif) {
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