anv/pipeline/gen7: Set the depth format in 3DSTATE_SF

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jason Ekstrand 2016-08-06 09:11:53 -07:00
parent 21d5c1be6a
commit 52fcc40760
3 changed files with 25 additions and 2 deletions

View file

@ -67,7 +67,8 @@ genX(graphics_pipeline_create)(
emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
assert(pCreateInfo->pRasterizationState);
emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
pass, subpass, extra);
emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);

View file

@ -119,7 +119,8 @@ genX(graphics_pipeline_create)(
assert(pCreateInfo->pInputAssemblyState);
emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
assert(pCreateInfo->pRasterizationState);
emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
pass, subpass, extra);
emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
emit_cb_state(pipeline, pCreateInfo->pColorBlendState,

View file

@ -365,6 +365,8 @@ static const uint32_t vk_to_gen_front_face[] = {
static void
emit_rs_state(struct anv_pipeline *pipeline,
const VkPipelineRasterizationStateCreateInfo *info,
const struct anv_render_pass *pass,
const struct anv_subpass *subpass,
const struct anv_graphics_pipeline_create_info *extra)
{
struct GENX(3DSTATE_SF) sf = {
@ -414,6 +416,25 @@ emit_rs_state(struct anv_pipeline *pipeline,
raster.GlobalDepthOffsetEnableWireframe = info->depthBiasEnable;
raster.GlobalDepthOffsetEnablePoint = info->depthBiasEnable;
#if GEN_GEN == 7
/* Gen7 requires that we provide the depth format in 3DSTATE_SF so that it
* can get the depth offsets correct.
*/
if (subpass->depth_stencil_attachment < pass->attachment_count) {
VkFormat vk_format =
pass->attachments[subpass->depth_stencil_attachment].format;
assert(vk_format_is_depth_or_stencil(vk_format));
if (vk_format_aspects(vk_format) & VK_IMAGE_ASPECT_DEPTH_BIT) {
enum isl_format isl_format =
anv_get_isl_format(&pipeline->device->info, vk_format,
VK_IMAGE_ASPECT_DEPTH_BIT,
VK_IMAGE_TILING_OPTIMAL);
sf.DepthBufferSurfaceFormat =
isl_format_get_depth_format(isl_format, false);
}
}
#endif
#if GEN_GEN >= 8
GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);