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etnaviv: align TS surface size to number of pixel pipes

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The TS surface gets cleared by a tiled RS fill. If the chip has
more than 1 pixel pipe the size of the TS surface needs to be
aligned so that each pipe address matches a tile start, otherwise
the RS will hang.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
This commit is contained in:
Lucas Stach 2016-11-21 12:27:47 +01:00
parent 37622ecc79
commit 52f6c8cc31
1 changed files with 2 additions and 1 deletions
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3
src/gallium/drivers/etnaviv/etnaviv_resource.c
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@ -52,7 +52,8 @@ etna_screen_resource_alloc_ts(struct pipe_screen *pscreen,
/* TS only for level 0 -- XXX is this formula correct? */
pixels = rsc->levels[0].layer_stride / util_format_get_blocksize(rsc->base.format);
ts_layer_stride = align(pixels * screen->specs.bits_per_tile / 0x80, 0x100);
ts_layer_stride = align(pixels * screen->specs.bits_per_tile / 0x80,
0x100 * screen->specs.pixel_pipes);
rt_ts_size = ts_layer_stride * rsc->base.array_size;
if (rt_ts_size == 0)
return true;