diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c
index e05ded312c3..a5ab1d4c184 100644
--- a/src/amd/common/ac_nir_lower_ngg.c
+++ b/src/amd/common/ac_nir_lower_ngg.c
@@ -570,7 +570,7 @@ emit_ngg_nogs_prim_export(nir_builder *b, lower_ngg_nogs_state *s, nir_ssa_def *
                             .memory_semantics = NIR_MEMORY_ACQ_REL,
                             .memory_modes = nir_var_mem_shared);
 
-         unsigned edge_flag_bits = (1u << 9) | (1u << 19) | (1u << 29);
+         unsigned edge_flag_bits = ac_get_all_edge_flag_bits();
          nir_ssa_def *mask = nir_imm_intN_t(b, ~edge_flag_bits, 32);
 
          unsigned edge_flag_offset = 0;
diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c
index fa264a2a156..39f23b071e6 100644
--- a/src/amd/common/ac_shader_util.c
+++ b/src/amd/common/ac_shader_util.c
@@ -1153,3 +1153,9 @@ union ac_hw_cache_flags ac_get_hw_cache_flags(const struct radeon_info *info,
 
    return result;
 }
+
+unsigned ac_get_all_edge_flag_bits(void)
+{
+   /* This will be extended in the future. */
+   return (1u << 9) | (1u << 19) | (1u << 29);
+}
diff --git a/src/amd/common/ac_shader_util.h b/src/amd/common/ac_shader_util.h
index 98a727fa4d3..01f816378ca 100644
--- a/src/amd/common/ac_shader_util.h
+++ b/src/amd/common/ac_shader_util.h
@@ -224,6 +224,8 @@ enum gl_access_qualifier ac_get_mem_access_flags(const nir_intrinsic_instr *inst
 union ac_hw_cache_flags ac_get_hw_cache_flags(const struct radeon_info *info,
                                               enum gl_access_qualifier access);
 
+unsigned ac_get_all_edge_flag_bits(void);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c
index fd04faf15c4..8cb9fc0e007 100644
--- a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c
+++ b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c
@@ -562,7 +562,12 @@ static bool lower_intrinsic(nir_builder *b, nir_instr *instr, struct lower_abi_s
       replacement = ac_nir_unpack_arg(b, &args->ac, args->ac.gs_tg_info, 22, 9);
       break;
    case nir_intrinsic_load_initial_edgeflags_amd:
-      if (stage == MESA_SHADER_VERTEX && !sel->info.base.vs.blit_sgprs_amd) {
+      if (shader->key.ge.opt.ngg_culling & SI_NGG_CULL_LINES ||
+          (shader->selector->stage == MESA_SHADER_VERTEX &&
+           shader->selector->info.base.vs.blit_sgprs_amd)) {
+         /* Line primitives and blits don't need edge flags. */
+         replacement = nir_imm_int(b, 0);
+      } else if (shader->selector->stage == MESA_SHADER_VERTEX) {
          /* Use the following trick to extract the edge flags:
           *   extracted = v_and_b32 gs_invocation_id, 0x700 ; get edge flags at bits 8, 9, 10
           *   shifted = v_mul_u32_u24 extracted, 0x80402u   ; shift the bits: 8->9, 9->19, 10->29
@@ -573,7 +578,11 @@ static bool lower_intrinsic(nir_builder *b, nir_instr *instr, struct lower_abi_s
          tmp = nir_imul_imm(b, tmp, 0x80402);
          replacement = nir_iand_imm(b, tmp, 0x20080200);
       } else {
-         replacement = nir_imm_int(b, 0);
+         /* Edge flags are always enabled when polygon mode is enabled, so we always have to
+          * return valid edge flags if the primitive type is not lines and if we are not blitting
+          * because the shader doesn't know when polygon mode is enabled.
+          */
+         replacement = nir_imm_int(b, ac_get_all_edge_flag_bits());
       }
       break;
    case nir_intrinsic_load_packed_passthrough_primitive_amd: