diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 02ce57bd0e4..29ec2767e3d 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -187,11 +187,6 @@ void *brw_state_batch(struct brw_context *brw, void gen4_init_vtable_surface_functions(struct brw_context *brw); uint32_t brw_get_surface_tiling_bits(uint32_t tiling); uint32_t brw_get_surface_num_multisamples(unsigned num_samples); -void brw_create_constant_surface(struct brw_context *brw, - drm_intel_bo *bo, - uint32_t offset, - int width, - uint32_t *out_offset); uint32_t brw_format_for_mesa_format(gl_format mesa_format); diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c index 2aefc0cc54a..6c0b690818f 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c @@ -68,9 +68,9 @@ brw_upload_vs_pull_constants(struct brw_context *brw) /* _NEW_PROGRAM_CONSTANTS */ drm_intel_bo_unreference(brw->vs.const_bo); + uint32_t size = brw->vs.prog_data->nr_pull_params * 4; brw->vs.const_bo = drm_intel_bo_alloc(intel->bufmgr, "vp_const_buffer", - brw->vs.prog_data->nr_pull_params * 4, - 64); + size, 64); drm_intel_gem_bo_map_gtt(brw->vs.const_bo); for (i = 0; i < brw->vs.prog_data->nr_pull_params; i++) { @@ -90,8 +90,7 @@ brw_upload_vs_pull_constants(struct brw_context *brw) drm_intel_gem_bo_unmap_gtt(brw->vs.const_bo); const int surf = SURF_INDEX_VERT_CONST_BUFFER; - intel->vtbl.create_constant_surface(brw, brw->vs.const_bo, 0, - ALIGN(brw->vs.prog_data->nr_pull_params, 4) / 4, + intel->vtbl.create_constant_surface(brw, brw->vs.const_bo, 0, size, &brw->vs.surf_offset[surf]); brw->state.dirty.brw |= BRW_NEW_VS_CONSTBUF; diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 657a56f06fd..b4369989ee3 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -899,15 +899,17 @@ brw_update_texture_surface(struct gl_context *ctx, * Create the constant buffer surface. Vertex/fragment shader constants will be * read from this buffer with Data Port Read instructions/messages. */ -void +static void brw_create_constant_surface(struct brw_context *brw, drm_intel_bo *bo, uint32_t offset, - int width, + uint32_t size, uint32_t *out_offset) { struct intel_context *intel = &brw->intel; - const GLint w = width - 1; + uint32_t stride = 16; + uint32_t elements = ALIGN(size, stride) / stride; + const GLint w = elements - 1; uint32_t *surf; surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, @@ -926,7 +928,7 @@ brw_create_constant_surface(struct brw_context *brw, ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT); surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT | - (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */ + (stride - 1) << BRW_SURFACE_PITCH_SHIFT); surf[4] = 0; surf[5] = 0; @@ -1073,8 +1075,7 @@ brw_upload_wm_pull_constants(struct brw_context *brw) } drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo); - intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0, - ALIGN(brw->wm.prog_data->nr_pull_params, 4) / 4, + intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0, size, &brw->wm.surf_offset[surf_index]); brw->state.dirty.brw |= BRW_NEW_SURFACES; @@ -1426,11 +1427,8 @@ brw_upload_ubo_surfaces(struct brw_context *brw, * glBindBufferRange case is undefined, we can just bind the whole buffer * glBindBufferBase wants and be a correct implementation. */ - int size = bo->size - binding->Offset; - size = ALIGN(size, 16) / 16; /* The interface takes a number of vec4s */ - intel->vtbl.create_constant_surface(brw, bo, binding->Offset, - size, + bo->size - binding->Offset, &surf_offsets[i]); } diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 2913fc6e61e..4d02ad2db29 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -372,11 +372,13 @@ static void gen7_create_constant_surface(struct brw_context *brw, drm_intel_bo *bo, uint32_t offset, - int width, + uint32_t size, uint32_t *out_offset) { struct intel_context *intel = &brw->intel; - const GLint w = width - 1; + uint32_t stride = 16; + uint32_t elements = ALIGN(size, stride) / stride; + const GLint w = elements - 1; uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, out_offset); @@ -392,7 +394,7 @@ gen7_create_constant_surface(struct brw_context *brw, surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT); surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH) | - (16 - 1); /* stride between samples */ + (stride - 1); if (intel->is_haswell) { surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 80e4cac131d..4d95eeaba46 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -201,7 +201,7 @@ struct intel_context void (*create_constant_surface)(struct brw_context *brw, drm_intel_bo *bo, uint32_t offset, - int width, + uint32_t size, uint32_t *out_offset); /** \} */ } vtbl;