From 529d7ebdcc38cd408022bb0e94d9da2f6de8214c Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 27 Feb 2024 14:15:27 +0100 Subject: [PATCH] radv: cleanup some functions that emit shader user SGPRs Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 61 ++++++++++++++------------------ 1 file changed, 27 insertions(+), 34 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index f5b69eaf4a7..7834d29d048 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -950,10 +950,11 @@ radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoint bi } static void -radv_emit_userdata_address(struct radv_device *device, struct radeon_cmdbuf *cs, struct radv_shader *shader, - uint32_t base_reg, int idx, uint64_t va) +radv_emit_userdata_address(const struct radv_device *device, struct radeon_cmdbuf *cs, const struct radv_shader *shader, + int idx, uint64_t va) { const struct radv_userdata_info *loc = &shader->info.user_sgprs_locs.shader_data[idx]; + const uint32_t base_reg = shader->info.user_data_0; if (loc->sgpr_idx == -1) return; @@ -979,10 +980,11 @@ radv_descriptor_get_va(const struct radv_descriptor_state *descriptors_state, un } static void -radv_emit_descriptor_pointers(struct radv_device *device, struct radeon_cmdbuf *cs, struct radv_shader *shader, - uint32_t sh_base, struct radv_descriptor_state *descriptors_state) +radv_emit_descriptor_pointers(const struct radv_device *device, struct radeon_cmdbuf *cs, + const struct radv_shader *shader, const struct radv_descriptor_state *descriptors_state) { - struct radv_userdata_locations *locs = &shader->info.user_sgprs_locs; + const struct radv_userdata_locations *locs = &shader->info.user_sgprs_locs; + const uint32_t sh_base = shader->info.user_data_0; unsigned mask = locs->descriptor_sets_enabled; mask &= descriptors_state->dirty & descriptors_state->valid; @@ -992,8 +994,8 @@ radv_emit_descriptor_pointers(struct radv_device *device, struct radeon_cmdbuf * u_bit_scan_consecutive_range(&mask, &start, &count); - struct radv_userdata_info *loc = &locs->descriptor_sets[start]; - unsigned sh_offset = sh_base + loc->sgpr_idx * 4; + const struct radv_userdata_info *loc = &locs->descriptor_sets[start]; + const unsigned sh_offset = sh_base + loc->sgpr_idx * 4; radv_emit_shader_pointer_head(cs, sh_offset, count, true); for (int i = 0; i < count; i++) { @@ -1234,10 +1236,11 @@ radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer) } static void -radv_emit_inline_push_consts(struct radv_device *device, struct radeon_cmdbuf *cs, const struct radv_shader *shader, - uint32_t base_reg, int idx, uint32_t *values) +radv_emit_inline_push_consts(const struct radv_device *device, struct radeon_cmdbuf *cs, + const struct radv_shader *shader, int idx, const uint32_t *values) { const struct radv_userdata_info *loc = &shader->info.user_sgprs_locs.shader_data[idx]; + const uint32_t base_reg = shader->info.user_data_0; if (loc->sgpr_idx == -1) return; @@ -5927,19 +5930,15 @@ radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer, VkPipeli if (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS) { for (unsigned s = MESA_SHADER_VERTEX; s <= MESA_SHADER_FRAGMENT; s++) if (radv_cmdbuf_has_stage(cmd_buffer, s)) - radv_emit_userdata_address(device, cs, cmd_buffer->state.shaders[s], - cmd_buffer->state.shaders[s]->info.user_data_0, AC_UD_INDIRECT_DESCRIPTOR_SETS, - va); + radv_emit_userdata_address(device, cs, cmd_buffer->state.shaders[s], AC_UD_INDIRECT_DESCRIPTOR_SETS, va); if (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_MESH)) radv_emit_userdata_address(device, cs, cmd_buffer->state.shaders[MESA_SHADER_MESH], - cmd_buffer->state.shaders[MESA_SHADER_MESH]->info.user_data_0, AC_UD_INDIRECT_DESCRIPTOR_SETS, va); if (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_TASK)) { radeon_check_space(device->ws, cmd_buffer->gang.cs, 3); radv_emit_userdata_address(device, cmd_buffer->gang.cs, cmd_buffer->state.shaders[MESA_SHADER_TASK], - cmd_buffer->state.shaders[MESA_SHADER_TASK]->info.user_data_0, AC_UD_INDIRECT_DESCRIPTOR_SETS, va); } } else { @@ -5947,8 +5946,7 @@ radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer, VkPipeli ? cmd_buffer->state.shaders[MESA_SHADER_COMPUTE] : cmd_buffer->state.rt_prolog; - radv_emit_userdata_address(device, cs, compute_shader, compute_shader->info.user_data_0, - AC_UD_INDIRECT_DESCRIPTOR_SETS, va); + radv_emit_userdata_address(device, cs, compute_shader, AC_UD_INDIRECT_DESCRIPTOR_SETS, va); } assert(cmd_buffer->cs->cdw <= cdw_max); @@ -5977,20 +5975,18 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags st ? cmd_buffer->state.shaders[MESA_SHADER_COMPUTE] : cmd_buffer->state.rt_prolog; - radv_emit_descriptor_pointers(device, cs, compute_shader, compute_shader->info.user_data_0, descriptors_state); + radv_emit_descriptor_pointers(device, cs, compute_shader, descriptors_state); } else { radv_foreach_stage(stage, stages & ~VK_SHADER_STAGE_TASK_BIT_EXT) { if (!cmd_buffer->state.shaders[stage]) continue; - radv_emit_descriptor_pointers(device, cs, cmd_buffer->state.shaders[stage], - cmd_buffer->state.shaders[stage]->info.user_data_0, descriptors_state); + radv_emit_descriptor_pointers(device, cs, cmd_buffer->state.shaders[stage], descriptors_state); } if (stages & VK_SHADER_STAGE_TASK_BIT_EXT) { radv_emit_descriptor_pointers(device, cmd_buffer->gang.cs, cmd_buffer->state.shaders[MESA_SHADER_TASK], - cmd_buffer->state.shaders[MESA_SHADER_TASK]->info.user_data_0, descriptors_state); } } @@ -6004,8 +6000,8 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags st } static void -radv_emit_all_inline_push_consts(struct radv_device *device, struct radeon_cmdbuf *cs, struct radv_shader *shader, - uint32_t base_reg, uint32_t *values, bool *need_push_constants) +radv_emit_all_inline_push_consts(const struct radv_device *device, struct radeon_cmdbuf *cs, + const struct radv_shader *shader, const uint32_t *values, bool *need_push_constants) { if (radv_get_user_sgpr_info(shader, AC_UD_PUSH_CONSTANTS)->sgpr_idx != -1) *need_push_constants |= true; @@ -6017,14 +6013,14 @@ radv_emit_all_inline_push_consts(struct radv_device *device, struct radeon_cmdbu const uint8_t base = ffs(mask) - 1; if (mask == u_bit_consecutive64(base, util_last_bit64(mask) - base)) { /* consecutive inline push constants */ - radv_emit_inline_push_consts(device, cs, shader, base_reg, AC_UD_INLINE_PUSH_CONSTANTS, values + base); + radv_emit_inline_push_consts(device, cs, shader, AC_UD_INLINE_PUSH_CONSTANTS, values + base); } else { /* sparse inline push constants */ uint32_t consts[AC_MAX_INLINE_PUSH_CONSTS]; unsigned num_consts = 0; u_foreach_bit64 (idx, mask) consts[num_consts++] = values[idx]; - radv_emit_inline_push_consts(device, cs, shader, base_reg, AC_UD_INLINE_PUSH_CONSTANTS, consts); + radv_emit_inline_push_consts(device, cs, shader, AC_UD_INLINE_PUSH_CONSTANTS, consts); } } @@ -6074,8 +6070,8 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag ? cmd_buffer->state.shaders[MESA_SHADER_COMPUTE] : cmd_buffer->state.rt_prolog; - radv_emit_all_inline_push_consts(device, cs, compute_shader, compute_shader->info.user_data_0, - (uint32_t *)cmd_buffer->push_constants, &need_push_constants); + radv_emit_all_inline_push_consts(device, cs, compute_shader, (uint32_t *)cmd_buffer->push_constants, + &need_push_constants); } else { radv_foreach_stage(stage, internal_stages & ~VK_SHADER_STAGE_TASK_BIT_EXT) { @@ -6084,13 +6080,12 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag if (!shader) continue; - radv_emit_all_inline_push_consts(device, cs, shader, shader->info.user_data_0, - (uint32_t *)cmd_buffer->push_constants, &need_push_constants); + radv_emit_all_inline_push_consts(device, cs, shader, (uint32_t *)cmd_buffer->push_constants, + &need_push_constants); } if (internal_stages & VK_SHADER_STAGE_TASK_BIT_EXT) { radv_emit_all_inline_push_consts(device, cmd_buffer->gang.cs, cmd_buffer->state.shaders[MESA_SHADER_TASK], - cmd_buffer->state.shaders[MESA_SHADER_TASK]->info.user_data_0, (uint32_t *)cmd_buffer->push_constants, &need_push_constants); } } @@ -6114,8 +6109,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag ? cmd_buffer->state.shaders[MESA_SHADER_COMPUTE] : cmd_buffer->state.rt_prolog; - radv_emit_userdata_address(device, cs, compute_shader, compute_shader->info.user_data_0, AC_UD_PUSH_CONSTANTS, - va); + radv_emit_userdata_address(device, cs, compute_shader, AC_UD_PUSH_CONSTANTS, va); } else { prev_shader = NULL; radv_foreach_stage(stage, internal_stages & ~VK_SHADER_STAGE_TASK_BIT_EXT) @@ -6124,7 +6118,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag /* Avoid redundantly emitting the address for merged stages. */ if (shader && shader != prev_shader) { - radv_emit_userdata_address(device, cs, shader, shader->info.user_data_0, AC_UD_PUSH_CONSTANTS, va); + radv_emit_userdata_address(device, cs, shader, AC_UD_PUSH_CONSTANTS, va); prev_shader = shader; } @@ -6132,7 +6126,6 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag if (internal_stages & VK_SHADER_STAGE_TASK_BIT_EXT) { radv_emit_userdata_address(device, cmd_buffer->gang.cs, cmd_buffer->state.shaders[MESA_SHADER_TASK], - cmd_buffer->state.shaders[MESA_SHADER_TASK]->info.user_data_0, AC_UD_PUSH_CONSTANTS, va); } } @@ -6342,7 +6335,7 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer) va = radv_buffer_get_va(cmd_buffer->upload.upload_bo); va += vb_offset; - radv_emit_userdata_address(device, cmd_buffer->cs, vs, vs->info.user_data_0, AC_UD_VS_VERTEX_BUFFERS, va); + radv_emit_userdata_address(device, cmd_buffer->cs, vs, AC_UD_VS_VERTEX_BUFFERS, va); cmd_buffer->state.vb_va = va; cmd_buffer->state.vb_size = vb_desc_alloc_size;