fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-22 13:08:09 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

aco/ra: fix compact_relocate_vars path for get_reg_for_operand

Browse source 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41018>
This commit is contained in:
Rhys Perry 2026-04-02 14:29:20 +01:00 • committed by Marge Bot
parent 7c4429d21a
commit 528aabb056
1 changed files with 20 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

38
src/amd/compiler/aco_register_allocation.cpp
View file

@ -2004,27 +2004,29 @@ get_reg(ra_ctx& ctx, const RegisterFile& reg_file, Temp temp,
unsigned def_size = info.rc.size();
std::vector<IDAndRegClass> def_vars;
for (Definition def : instr->definitions) {
if (def.isPrecolored()) {
assert(!regs.contains({def.physReg(), def.size()}));
continue;
}
if (ctx.assignments[def.tempId()].assigned && def.regClass().type() == info.rc.type()) {
def_size += def.regClass().size();
def_vars.emplace_back(def.tempId(), def.regClass());
}
}
unsigned killed_op_size = 0;
std::vector<IDAndRegClass> killed_op_vars;
for (Operand op : instr->operands) {
if (op.isPrecolored()) {
assert(!regs.contains({op.physReg(), op.size()}));
continue;
if (operand_index < 0) {
for (Definition def : instr->definitions) {
if (def.isPrecolored()) {
assert(!regs.contains({def.physReg(), def.size()}));
continue;
}
if (ctx.assignments[def.tempId()].assigned && def.regClass().type() == info.rc.type()) {
def_size += def.regClass().size();
def_vars.emplace_back(def.tempId(), def.regClass());
}
}
if (op.isTemp() && op.isFirstKillBeforeDef() && op.regClass().type() == info.rc.type()) {
killed_op_size += op.regClass().size();
killed_op_vars.emplace_back(op.tempId(), op.regClass());
for (Operand op : instr->operands) {
if (op.isPrecolored()) {
assert(!regs.contains({op.physReg(), op.size()}));
continue;
}
if (op.isTemp() && op.isFirstKillBeforeDef() && op.regClass().type() == info.rc.type()) {
killed_op_size += op.regClass().size();
killed_op_vars.emplace_back(op.tempId(), op.regClass());
}
}
}