From 527ae448e5fa67dc32926161bf6db6f14124feac Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Wed, 16 Jul 2025 23:29:18 +0300 Subject: [PATCH] brw/nir/rt: ensure we can load 2 RT_DISPATCH_GLOBALS Each group of 16 lanes inside a SIMD32 shader will load different globals. In SIMD8/16 shaders, the divergence analysis will turn this load into nir_load_global_constant_uniform_block_intel. Signed-off-by: Lionel Landwerlin Cc: mesa-stable Reviewed-by: Sagar Ghuge Part-of: --- src/intel/compiler/brw/brw_nir_rt_builder.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw/brw_nir_rt_builder.h b/src/intel/compiler/brw/brw_nir_rt_builder.h index ead512ac7c5..d66fa897e4c 100644 --- a/src/intel/compiler/brw/brw_nir_rt_builder.h +++ b/src/intel/compiler/brw/brw_nir_rt_builder.h @@ -62,7 +62,7 @@ brw_nir_rt_store(nir_builder *b, nir_def *addr, unsigned align, static inline nir_def * brw_nir_rt_load_const(nir_builder *b, unsigned components, nir_def *addr) { - return nir_load_global_constant_uniform_block_intel( + return nir_build_load_global_constant( b, components, 32, addr, .access = ACCESS_CAN_REORDER | ACCESS_NON_WRITEABLE, .align_mul = 64);