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intel/compiler: Add 64-bit A64 float logical opcode support

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Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12566>
This commit is contained in:
Sagar Ghuge 2021-08-26 10:13:34 -07:00 • committed by Marge Bot
parent 7f2395046f
commit 527468f56f
4 changed files with 12 additions and 0 deletions
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1
src/intel/compiler/brw_eu_defines.h
View file

@ -442,6 +442,7 @@ enum opcode {
SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL,
SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL,
SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL,
SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL,
SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,

4
src/intel/compiler/brw_fs.cpp
View file

@ -884,6 +884,7 @@ fs_inst::components_read(unsigned i) const
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL:
assert(src[2].file == IMM);
if (i == 1) {
/* Data source */
@ -6298,6 +6299,7 @@ lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst)
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL: {
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL:
/* Bspec: Atomic instruction -> Cache section:
*
* Atomic messages are always forced to "un-cacheable" in the L1
@ -6933,6 +6935,7 @@ fs_visitor::lower_logical_sends()
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL:
if (devinfo->has_lsc) {
lower_lsc_a64_logical_send(ibld, inst);
break;
@ -7560,6 +7563,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL:
return 8;
case SHADER_OPCODE_URB_READ_SIMD8:

4
src/intel/compiler/brw_fs_nir.cpp
View file

@ -5984,6 +5984,10 @@ fs_visitor::nir_emit_global_atomic_float(const fs_builder &bld,
bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL,
dest, addr, data, brw_imm_ud(op));
break;
case 64:
bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL,
dest, addr, data, brw_imm_ud(op));
break;
default:
unreachable("Unsupported bit size");
}

3
src/intel/compiler/brw_shader.cpp
View file

@ -331,6 +331,8 @@ brw_instruction_name(const struct intel_device_info *devinfo, enum opcode op)
return "a64_untyped_atomic_float16_logical";
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL:
return "a64_untyped_atomic_float32_logical";
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL:
return "a64_untyped_atomic_float64_logical";
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
return "typed_atomic_logical";
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
@ -1122,6 +1124,7 @@ backend_instruction::has_side_effects() const
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL:
case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: