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intel/fs: Fix MOV_INDIRECT and BROADCAST of Q types on Gen11+

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The immediate case is pretty uncommon to see but it can happen, in
theory.  BROADCAST is typically used to uniformize values and those are
usually 32-bit.  However, it does come up in some subgroup ops.

Fixes: 49c21802cb "intel/compiler: Split has_64bit_types into float/int"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6211>
(cherry picked from commit cccb497d3c)
This commit is contained in:
Jason Ekstrand 2020-07-17 16:22:11 -05:00 • committed by Dylan Baker
parent 3d1a71aa2b
commit 525a5b763d
3 changed files with 24 additions and 6 deletions
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2
.pick_status.json
View file

@ -121,7 +121,7 @@
"description": "intel/fs: Fix MOV_INDIRECT and BROADCAST of Q types on Gen11+",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "49c21802cbca8240b272318759b1e472142929e6"
},

18
src/intel/compiler/brw_eu_emit.c
View file

@ -3361,9 +3361,18 @@ brw_broadcast(struct brw_codegen *p,
* asserting would be mean.
*/
const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0;
brw_MOV(p, dst,
(align1 ? stride(suboffset(src, i), 0, 1, 0) :
stride(suboffset(src, 4 * i), 0, 4, 1)));
src = align1 ? stride(suboffset(src, i), 0, 1, 0) :
stride(suboffset(src, 4 * i), 0, 4, 1);
if (type_sz(src.type) > 4 && !devinfo->has_64bit_float) {
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
subscript(src, BRW_REGISTER_TYPE_D, 0));
brw_set_default_swsb(p, tgl_swsb_null());
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
subscript(src, BRW_REGISTER_TYPE_D, 1));
} else {
brw_MOV(p, dst, src);
}
} else {
/* From the Haswell PRM section "Register Region Restrictions":
*
@ -3412,7 +3421,8 @@ brw_broadcast(struct brw_codegen *p,
/* Use indirect addressing to fetch the specified component. */
if (type_sz(src.type) > 4 &&
(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
/* From the Cherryview PRM Vol 7. "Register Region Restrictions":
*
* "When source or destination datatype is 64b or operation is

10
src/intel/compiler/brw_fs_generator.cpp
View file

@ -468,7 +468,15 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
reg.nr = imm_byte_offset / REG_SIZE;
reg.subnr = imm_byte_offset % REG_SIZE;
brw_MOV(p, dst, reg);
if (type_sz(reg.type) > 4 && !devinfo->has_64bit_float) {
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
subscript(reg, BRW_REGISTER_TYPE_D, 0));
brw_set_default_swsb(p, tgl_swsb_null());
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
subscript(reg, BRW_REGISTER_TYPE_D, 1));
} else {
brw_MOV(p, dst, reg);
}
} else {
/* Prior to Broadwell, there are only 8 address registers. */
assert(inst->exec_size <= 8 || devinfo->gen >= 8);