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radv: Break up radv_shader_nir_to_asm

Browse source 
radv_shader_nir_to_asm actually had 3 functions: compiling the NIR to
asm, uploading the shaders and generating debug info for them.
This reduces the functionality of radv_shader_nir_to_asm to only compile
NIR to asm. Uploading the shader and generating debug info is split into
separate functions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23516>
This commit is contained in:
Friedrich Vock 2023-06-07 11:12:51 +02:00 • committed by Marge Bot
parent 878a731c77
commit 51f2fa1a5e
6 changed files with 70 additions and 50 deletions
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10
src/amd/vulkan/radv_pipeline_cache.c
View file

@ -155,7 +155,7 @@ radv_shader_deserialize(struct vk_pipeline_cache *cache, const void *key_data, s
const struct radv_shader_binary *binary = blob_read_bytes(blob, sizeof(struct radv_shader_binary));
assert(key_size == SHA1_DIGEST_LENGTH);
struct radv_shader *shader = radv_shader_create(device, binary);
struct radv_shader *shader = radv_shader_create_uncached(device, binary);
if (!shader)
return NULL;
@ -196,11 +196,11 @@ radv_shader_serialize(struct vk_pipeline_cache_object *object, struct blob *blob
}
struct radv_shader *
radv_shader_create_cached(struct radv_device *device, struct vk_pipeline_cache *cache,
const struct radv_shader_binary *binary)
radv_shader_create(struct radv_device *device, struct vk_pipeline_cache *cache, const struct radv_shader_binary *binary,
bool skip_cache)
{
if (radv_is_cache_disabled(device))
return radv_shader_create(device, binary);
if (radv_is_cache_disabled(device) || skip_cache)
return radv_shader_create_uncached(device, binary);
if (!cache)
cache = device->mem_cache;

9
src/amd/vulkan/radv_pipeline_compute.c
View file

@ -203,9 +203,14 @@ radv_compute_pipeline_compile(struct radv_compute_pipeline *pipeline, struct rad
nir_print_shader(cs_stage.nir, stderr);
/* Compile NIR shader to AMD assembly. */
bool dump_shader = radv_can_dump_shader(device, cs_stage.nir, false);
binaries[MESA_SHADER_COMPUTE] = radv_shader_nir_to_asm(device, &cs_stage, &cs_stage.nir, 1, pipeline_key,
keep_executable_info, keep_statistic_info);
pipeline->base.shaders[MESA_SHADER_COMPUTE] =
radv_shader_nir_to_asm(device, cache, &cs_stage, &cs_stage.nir, 1, pipeline_key, keep_executable_info,
keep_statistic_info, &binaries[MESA_SHADER_COMPUTE]);
radv_shader_create(device, cache, binaries[MESA_SHADER_COMPUTE], keep_executable_info || dump_shader);
radv_shader_generate_debug_info(device, dump_shader, binaries[MESA_SHADER_COMPUTE],
pipeline->base.shaders[MESA_SHADER_COMPUTE], &cs_stage.nir, 1, &cs_stage.info);
cs_stage.feedback.duration += os_time_get_nano() - stage_start;

20
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -2217,8 +2217,15 @@ radv_pipeline_create_gs_copy_shader(struct radv_device *device, struct radv_pipe
.optimisations_disabled = pipeline_key->optimisations_disabled,
};
return radv_shader_nir_to_asm(device, cache, &gs_copy_stage, &nir, 1, &key, keep_executable_info,
keep_statistic_info, gs_copy_binary);
bool dump_shader = radv_can_dump_shader(device, nir, true);
*gs_copy_binary =
radv_shader_nir_to_asm(device, &gs_copy_stage, &nir, 1, &key, keep_executable_info, keep_statistic_info);
struct radv_shader *copy_shader =
radv_shader_create(device, cache, *gs_copy_binary, keep_executable_info || dump_shader);
if (copy_shader)
radv_shader_generate_debug_info(device, dump_shader, *gs_copy_binary, copy_shader, &nir, 1, &gs_copy_stage.info);
return copy_shader;
}
static void
@ -2254,8 +2261,13 @@ radv_pipeline_nir_to_asm(struct radv_device *device, struct radv_graphics_pipeli
int64_t stage_start = os_time_get_nano();
pipeline->base.shaders[s] = radv_shader_nir_to_asm(device, cache, &stages[s], shaders, shader_count, pipeline_key,
keep_executable_info, keep_statistic_info, &binaries[s]);
bool dump_shader = radv_can_dump_shader(device, shaders[0], false);
binaries[s] = radv_shader_nir_to_asm(device, &stages[s], shaders, shader_count, pipeline_key,
keep_executable_info, keep_statistic_info);
pipeline->base.shaders[s] = radv_shader_create(device, cache, binaries[s], keep_executable_info || dump_shader);
radv_shader_generate_debug_info(device, dump_shader, binaries[s], pipeline->base.shaders[s], shaders,
shader_count, &stages[s].info);
if (s == MESA_SHADER_GEOMETRY && !stages[s].info.is_ngg) {
pipeline->base.gs_copy_shader =

12
src/amd/vulkan/radv_pipeline_rt.c
View file

@ -353,16 +353,22 @@ radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache,
nir_print_shader(temp_stage.nir, stderr);
}
bool dump_shader = radv_can_dump_shader(device, shaders[0], false);
/* Compile NIR shader to AMD assembly. */
struct radv_shader *shader;
shader = radv_shader_nir_to_asm(device, cache, stage, shaders, num_shaders, pipeline_key, keep_executable_info,
keep_statistic_info, &binary);
binary = radv_shader_nir_to_asm(device, stage, shaders, num_shaders, pipeline_key, keep_executable_info,
keep_statistic_info);
struct radv_shader *shader = radv_shader_create(device, cache, binary, keep_executable_info || dump_shader);
if (shader) {
radv_shader_generate_debug_info(device, dump_shader, binary, shader, shaders, num_shaders, &stage->info);
if (shader && keep_executable_info && stage->spirv.size) {
shader->spirv = malloc(stage->spirv.size);
memcpy(shader->spirv, stage->spirv.data, stage->spirv.size);
shader->spirv_size = stage->spirv.size;
}
}
free(binary);

38
src/amd/vulkan/radv_shader.c
View file

@ -2002,7 +2002,7 @@ radv_shader_dma_submit(struct radv_device *device, struct radv_shader_dma_submis
}
struct radv_shader *
radv_shader_create(struct radv_device *device, const struct radv_shader_binary *binary)
radv_shader_create_uncached(struct radv_device *device, const struct radv_shader_binary *binary)
{
struct radv_shader *shader = calloc(1, sizeof(struct radv_shader));
if (!shader)
@ -2334,11 +2334,10 @@ shader_compile(struct radv_device *device, struct nir_shader *const *shaders, in
return binary;
}
struct radv_shader *
radv_shader_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache,
struct radv_pipeline_stage *pl_stage, struct nir_shader *const *shaders, int shader_count,
const struct radv_pipeline_key *key, bool keep_shader_info, bool keep_statistic_info,
struct radv_shader_binary **binary_out)
struct radv_shader_binary *
radv_shader_nir_to_asm(struct radv_device *device, struct radv_pipeline_stage *pl_stage,
struct nir_shader *const *shaders, int shader_count, const struct radv_pipeline_key *key,
bool keep_shader_info, bool keep_statistic_info)
{
gl_shader_stage stage = shaders[shader_count - 1]->info.stage;
struct radv_shader_info *info = &pl_stage->info;
@ -2351,32 +2350,23 @@ radv_shader_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cac
struct radv_shader_binary *binary =
shader_compile(device, shaders, shader_count, stage, info, &pl_stage->args, &options);
struct radv_shader *shader;
if (keep_shader_info || options.dump_shader) {
/* skip cache insertion and directly create shader */
shader = radv_shader_create(device, binary);
} else {
shader = radv_shader_create_cached(device, cache, binary);
}
if (!shader) {
free(binary);
return NULL;
return binary;
}
if (keep_shader_info || options.dump_shader) {
void
radv_shader_generate_debug_info(struct radv_device *device, bool dump_shader, struct radv_shader_binary *binary,
struct radv_shader *shader, struct nir_shader *const *shaders, int shader_count,
struct radv_shader_info *info)
{
radv_capture_shader_executable_info(device, shader, shaders, shader_count, binary);
}
if (options.dump_shader) {
if (dump_shader) {
fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
for (int i = 1; i < shader_count; ++i)
fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
fprintf(stderr, "\ndisasm:\n%s\n", shader->disasm_string);
}
*binary_out = binary;
return shader;
}
struct radv_shader *
@ -2398,7 +2388,7 @@ radv_create_trap_handler_shader(struct radv_device *device)
radv_declare_shader_args(device, &key, &info, stage, MESA_SHADER_NONE, &args);
struct radv_shader_binary *binary = shader_compile(device, &b.shader, 1, stage, &info, &args, &options);
struct radv_shader *shader = radv_shader_create(device, binary);
struct radv_shader *shader = radv_shader_create_uncached(device, binary);
ralloc_free(b.shader);
free(binary);
@ -2478,7 +2468,7 @@ radv_create_rt_prolog(struct radv_device *device)
binary->info = info;
radv_postprocess_binary_config(device, binary, &in_args);
prolog = radv_shader_create(device, binary);
prolog = radv_shader_create_uncached(device, binary);
if (!prolog)
goto done;

17
src/amd/vulkan/radv_shader.h
View file

@ -621,15 +621,22 @@ void radv_destroy_shader_upload_queue(struct radv_device *device);
struct radv_shader_args;
struct radv_shader *radv_shader_create(struct radv_device *device, const struct radv_shader_binary *binary);
struct radv_shader *radv_shader_create(struct radv_device *device, struct vk_pipeline_cache *cache,
const struct radv_shader_binary *binary, bool skip_cache);
struct radv_shader *radv_shader_create_uncached(struct radv_device *device, const struct radv_shader_binary *binary);
struct radv_shader *radv_shader_create_cached(struct radv_device *device, struct vk_pipeline_cache *cache,
const struct radv_shader_binary *binary);
struct radv_shader *radv_shader_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache,
struct radv_pipeline_stage *stage, struct nir_shader *const *shaders,
int shader_count, const struct radv_pipeline_key *key, bool keep_shader_info,
bool keep_statistic_info, struct radv_shader_binary **binary_out);
struct radv_shader_binary *radv_shader_nir_to_asm(struct radv_device *device, struct radv_pipeline_stage *pl_stage,
struct nir_shader *const *shaders, int shader_count,
const struct radv_pipeline_key *key, bool keep_shader_info,
bool keep_statistic_info);
void radv_shader_generate_debug_info(struct radv_device *device, bool dump_shader, struct radv_shader_binary *binary,
struct radv_shader *shader, struct nir_shader *const *shaders, int shader_count,
struct radv_shader_info *info);
VkResult radv_shader_wait_for_upload(struct radv_device *device, uint64_t seq);