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ilo: use ilo_dev_info in GPE and 3D pipeline

Browse source 
We need only dev->gen and dev->gt, but it makes sense to expose other
information to the pipeline.
This commit is contained in:
Chia-I Wu 2013-04-29 09:58:51 +08:00
parent bb1f635dcc
commit 51d749e7e2
12 changed files with 587 additions and 597 deletions
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4
src/gallium/drivers/ilo/ilo_3d.c
View file

@ -313,7 +313,7 @@ ilo_3d_post_cp_flush(struct ilo_3d *hw3d)
* Create a 3D context.
*/
struct ilo_3d *
ilo_3d_create(struct ilo_cp *cp, int gen, int gt)
ilo_3d_create(struct ilo_cp *cp, const struct ilo_dev_info *dev)
{
struct ilo_3d *hw3d;
@ -329,7 +329,7 @@ ilo_3d_create(struct ilo_cp *cp, int gen, int gt)
list_inithead(&hw3d->prim_generated_queries);
list_inithead(&hw3d->prim_emitted_queries);
hw3d->pipeline = ilo_3d_pipeline_create(cp, gen, gt);
hw3d->pipeline = ilo_3d_pipeline_create(cp, dev);
if (!hw3d->pipeline) {
FREE(hw3d);
return NULL;

2
src/gallium/drivers/ilo/ilo_3d.h
View file

@ -58,7 +58,7 @@ struct ilo_3d {
};
struct ilo_3d *
ilo_3d_create(struct ilo_cp *cp, int gen, int gt);
ilo_3d_create(struct ilo_cp *cp, const struct ilo_dev_info *dev);
void
ilo_3d_destroy(struct ilo_3d *hw3d);

11
src/gallium/drivers/ilo/ilo_3d_pipeline.c
View file

@ -64,7 +64,7 @@ static const struct sample_position sample_position_8x[8] = {
};
struct ilo_3d_pipeline *
ilo_3d_pipeline_create(struct ilo_cp *cp, int gen, int gt)
ilo_3d_pipeline_create(struct ilo_cp *cp, const struct ilo_dev_info *dev)
{
struct ilo_3d_pipeline *p;
int i;
@ -74,9 +74,9 @@ ilo_3d_pipeline_create(struct ilo_cp *cp, int gen, int gt)
return NULL;
p->cp = cp;
p->gen = gen;
p->dev = dev;
switch (p->gen) {
switch (p->dev->gen) {
case ILO_GEN(6):
ilo_3d_pipeline_init_gen6(p);
break;
@ -90,9 +90,6 @@ ilo_3d_pipeline_create(struct ilo_cp *cp, int gen, int gt)
break;
}
p->gpe.gen = p->gen;
p->gpe.gt = gt;
p->invalidate_flags = ILO_3D_PIPELINE_INVALIDATE_ALL;
p->workaround_bo = p->cp->winsys->alloc_buffer(p->cp->winsys,
@ -138,7 +135,7 @@ static void
handle_invalid_batch_bo(struct ilo_3d_pipeline *p, bool unset)
{
if (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_BATCH_BO) {
if (p->gen == ILO_GEN(6))
if (p->dev->gen == ILO_GEN(6))
p->state.has_gen6_wa_pipe_control = false;
if (unset)

6
src/gallium/drivers/ilo/ilo_3d_pipeline.h
View file

@ -59,9 +59,7 @@ enum ilo_3d_pipeline_action {
*/
struct ilo_3d_pipeline {
struct ilo_cp *cp;
int gen;
struct ilo_gpe gpe;
const struct ilo_dev_info *dev;
uint32_t invalidate_flags;
@ -235,7 +233,7 @@ struct ilo_3d_pipeline {
};
struct ilo_3d_pipeline *
ilo_3d_pipeline_create(struct ilo_cp *cp, int gen, int gt);
ilo_3d_pipeline_create(struct ilo_cp *cp, const struct ilo_dev_info *dev);
void
ilo_3d_pipeline_destroy(struct ilo_3d_pipeline *pipeline);

2
src/gallium/drivers/ilo/ilo_3d_pipeline_dump.c
View file

@ -520,7 +520,7 @@ static void dump_binding_table(struct brw_context *brw, uint32_t offset,
static void
init_brw(struct brw_context *brw, struct ilo_3d_pipeline *p)
{
brw->intel.gen = ILO_GEN_GET_MAJOR(p->gen);
brw->intel.gen = ILO_GEN_GET_MAJOR(p->dev->gen);
brw->intel.batch.bo_dst.virtual = p->cp->bo->get_virtual(p->cp->bo);
brw->intel.batch.bo = &brw->intel.batch.bo_dst;
}

188
src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c
View file

@ -47,7 +47,7 @@ static void
gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline *p,
bool caller_post_sync)
{
assert(p->gen == ILO_GEN(6));
assert(p->dev->gen == ILO_GEN(6));
/* emit once */
if (p->state.has_gen6_wa_pipe_control)
@ -63,7 +63,7 @@ gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline *p,
*
* The workaround below necessitates this workaround.
*/
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD,
NULL, 0, false, p->cp);
@ -82,7 +82,7 @@ gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline *p,
* "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
* PIPE_CONTROL with any non-zero post-sync-op is required."
*/
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_WRITE_IMMEDIATE,
p->workaround_bo, 0, false, p->cp);
}
@ -90,7 +90,7 @@ gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline *p,
static void
gen6_wa_pipe_control_wm_multisample_flush(struct ilo_3d_pipeline *p)
{
assert(p->gen == ILO_GEN(6));
assert(p->dev->gen == ILO_GEN(6));
gen6_wa_pipe_control_post_sync(p, false);
@ -102,7 +102,7 @@ gen6_wa_pipe_control_wm_multisample_flush(struct ilo_3d_pipeline *p)
* requires driver to send a PIPE_CONTROL with a CS stall along with a
* Depth Flush prior to this command."
*/
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_CS_STALL,
0, 0, false, p->cp);
@ -111,7 +111,7 @@ gen6_wa_pipe_control_wm_multisample_flush(struct ilo_3d_pipeline *p)
static void
gen6_wa_pipe_control_wm_depth_flush(struct ilo_3d_pipeline *p)
{
assert(p->gen == ILO_GEN(6));
assert(p->dev->gen == ILO_GEN(6));
gen6_wa_pipe_control_post_sync(p, false);
@ -120,15 +120,15 @@ gen6_wa_pipe_control_wm_depth_flush(struct ilo_3d_pipeline *p)
* to emit a sequence of PIPE_CONTROLs prior to emitting depth related
* commands.
*/
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL,
NULL, 0, false, p->cp);
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_CACHE_FLUSH,
NULL, 0, false, p->cp);
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL,
NULL, 0, false, p->cp);
}
@ -136,7 +136,7 @@ gen6_wa_pipe_control_wm_depth_flush(struct ilo_3d_pipeline *p)
static void
gen6_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
{
assert(p->gen == ILO_GEN(6));
assert(p->dev->gen == ILO_GEN(6));
/* the post-sync workaround should cover this already */
if (p->state.has_gen6_wa_pipe_control)
@ -149,7 +149,7 @@ gen6_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
* field set (DW1 Bit 1), must be issued prior to any change to the
* value in this field (Maximum Number of Threads in 3DSTATE_WM)"
*/
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_STALL_AT_SCOREBOARD,
NULL, 0, false, p->cp);
@ -158,7 +158,7 @@ gen6_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
static void
gen6_wa_pipe_control_vs_const_flush(struct ilo_3d_pipeline *p)
{
assert(p->gen == ILO_GEN(6));
assert(p->dev->gen == ILO_GEN(6));
gen6_wa_pipe_control_post_sync(p, false);
@ -167,7 +167,7 @@ gen6_wa_pipe_control_vs_const_flush(struct ilo_3d_pipeline *p)
* PIPE_CONTROL after 3DSTATE_CONSTANT_VS so that the command is kept being
* buffered by VS FF, to the point that the FF dies.
*/
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_INSTRUCTION_FLUSH |
PIPE_CONTROL_STATE_CACHE_INVALIDATE,
@ -183,10 +183,10 @@ gen6_pipeline_common_select(struct ilo_3d_pipeline *p,
{
/* PIPELINE_SELECT */
if (session->hw_ctx_changed) {
if (p->gen == ILO_GEN(6))
if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
p->gen6_PIPELINE_SELECT(&p->gpe, 0x0, p->cp);
p->gen6_PIPELINE_SELECT(p->dev, 0x0, p->cp);
}
}
@ -197,10 +197,10 @@ gen6_pipeline_common_sip(struct ilo_3d_pipeline *p,
{
/* STATE_SIP */
if (session->hw_ctx_changed) {
if (p->gen == ILO_GEN(6))
if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
p->gen6_STATE_SIP(&p->gpe, 0, p->cp);
p->gen6_STATE_SIP(p->dev, 0, p->cp);
}
}
@ -211,10 +211,10 @@ gen6_pipeline_common_base_address(struct ilo_3d_pipeline *p,
{
/* STATE_BASE_ADDRESS */
if (session->state_bo_changed || session->instruction_bo_changed) {
if (p->gen == ILO_GEN(6))
if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
p->gen6_STATE_BASE_ADDRESS(&p->gpe,
p->gen6_STATE_BASE_ADDRESS(p->dev,
NULL, p->cp->bo, p->cp->bo, NULL, ilo->shader_cache->bo,
0, 0, 0, 0, p->cp);
@ -309,7 +309,7 @@ gen6_pipeline_common_urb(struct ilo_3d_pipeline *p,
gs_total_size = 0;
}
p->gen6_3DSTATE_URB(&p->gpe, vs_total_size, gs_total_size,
p->gen6_3DSTATE_URB(p->dev, vs_total_size, gs_total_size,
vs_entry_size, gs_entry_size, p->cp);
/*
@ -335,7 +335,7 @@ gen6_pipeline_common_pointers_1(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_VIEWPORT_STATE_POINTERS */
if (session->viewport_state_changed) {
p->gen6_3DSTATE_VIEWPORT_STATE_POINTERS(&p->gpe,
p->gen6_3DSTATE_VIEWPORT_STATE_POINTERS(p->dev,
p->state.CLIP_VIEWPORT,
p->state.SF_VIEWPORT,
p->state.CC_VIEWPORT, p->cp);
@ -351,7 +351,7 @@ gen6_pipeline_common_pointers_2(struct ilo_3d_pipeline *p,
if (session->cc_state_blend_changed ||
session->cc_state_dsa_changed ||
session->cc_state_cc_changed) {
p->gen6_3DSTATE_CC_STATE_POINTERS(&p->gpe,
p->gen6_3DSTATE_CC_STATE_POINTERS(p->dev,
p->state.BLEND_STATE,
p->state.DEPTH_STENCIL_STATE,
p->state.COLOR_CALC_STATE, p->cp);
@ -361,7 +361,7 @@ gen6_pipeline_common_pointers_2(struct ilo_3d_pipeline *p,
if (session->sampler_state_vs_changed ||
session->sampler_state_gs_changed ||
session->sampler_state_fs_changed) {
p->gen6_3DSTATE_SAMPLER_STATE_POINTERS(&p->gpe,
p->gen6_3DSTATE_SAMPLER_STATE_POINTERS(p->dev,
p->state.vs.SAMPLER_STATE,
0,
p->state.wm.SAMPLER_STATE, p->cp);
@ -375,7 +375,7 @@ gen6_pipeline_common_pointers_3(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_SCISSOR_STATE_POINTERS */
if (session->scissor_state_changed) {
p->gen6_3DSTATE_SCISSOR_STATE_POINTERS(&p->gpe,
p->gen6_3DSTATE_SCISSOR_STATE_POINTERS(p->dev,
p->state.SCISSOR_RECT, p->cp);
}
@ -383,7 +383,7 @@ gen6_pipeline_common_pointers_3(struct ilo_3d_pipeline *p,
if (session->binding_table_vs_changed ||
session->binding_table_gs_changed ||
session->binding_table_fs_changed) {
p->gen6_3DSTATE_BINDING_TABLE_POINTERS(&p->gpe,
p->gen6_3DSTATE_BINDING_TABLE_POINTERS(p->dev,
p->state.vs.BINDING_TABLE_STATE,
p->state.gs.BINDING_TABLE_STATE,
p->state.wm.BINDING_TABLE_STATE, p->cp);
@ -397,13 +397,13 @@ gen6_pipeline_vf(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_INDEX_BUFFER */
if (DIRTY(INDEX_BUFFER)) {
p->gen6_3DSTATE_INDEX_BUFFER(&p->gpe,
p->gen6_3DSTATE_INDEX_BUFFER(p->dev,
&ilo->index_buffer, false, p->cp);
}
/* 3DSTATE_VERTEX_BUFFERS */
if (DIRTY(VERTEX_BUFFERS)) {
p->gen6_3DSTATE_VERTEX_BUFFERS(&p->gpe,
p->gen6_3DSTATE_VERTEX_BUFFERS(p->dev,
ilo->vertex_buffers.buffers, NULL,
(1 << ilo->vertex_buffers.num_buffers) - 1, p->cp);
}
@ -426,7 +426,7 @@ gen6_pipeline_vf(struct ilo_3d_pipeline *p,
prepend_generate_ids = (info->has_instanceid || info->has_vertexid);
}
p->gen6_3DSTATE_VERTEX_ELEMENTS(&p->gpe,
p->gen6_3DSTATE_VERTEX_ELEMENTS(p->dev,
ive->elements, ive->num_elements,
last_velement_edgeflag, prepend_generate_ids, p->cp);
}
@ -439,7 +439,7 @@ gen6_pipeline_vf_statistics(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_VF_STATISTICS */
if (session->hw_ctx_changed)
p->gen6_3DSTATE_VF_STATISTICS(&p->gpe, false, p->cp);
p->gen6_3DSTATE_VF_STATISTICS(p->dev, false, p->cp);
}
void
@ -448,7 +448,7 @@ gen6_pipeline_vf_draw(struct ilo_3d_pipeline *p,
struct gen6_pipeline_session *session)
{
/* 3DPRIMITIVE */
p->gen6_3DPRIMITIVE(&p->gpe, session->info, false, p->cp);
p->gen6_3DPRIMITIVE(p->dev, session->info, false, p->cp);
p->state.has_gen6_wa_pipe_control = false;
}
@ -464,12 +464,12 @@ gen6_pipeline_vs(struct ilo_3d_pipeline *p,
* the classic i965 does this in upload_vs_state(), citing a spec that I
* cannot find
*/
if (emit_3dstate_vs && p->gen == ILO_GEN(6))
if (emit_3dstate_vs && p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
/* 3DSTATE_CONSTANT_VS */
if (emit_3dstate_constant_vs) {
p->gen6_3DSTATE_CONSTANT_VS(&p->gpe,
p->gen6_3DSTATE_CONSTANT_VS(p->dev,
&p->state.vs.PUSH_CONSTANT_BUFFER,
&p->state.vs.PUSH_CONSTANT_BUFFER_size,
1, p->cp);
@ -480,11 +480,11 @@ gen6_pipeline_vs(struct ilo_3d_pipeline *p,
const struct ilo_shader *vs = (ilo->vs)? ilo->vs->shader : NULL;
const int num_samplers = ilo->samplers[PIPE_SHADER_VERTEX].num_samplers;
p->gen6_3DSTATE_VS(&p->gpe,
p->gen6_3DSTATE_VS(p->dev,
vs, ilo->max_vs_threads, num_samplers, p->cp);
}
if (emit_3dstate_constant_vs && p->gen == ILO_GEN(6))
if (emit_3dstate_constant_vs && p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_vs_const_flush(p);
}
@ -495,7 +495,7 @@ gen6_pipeline_gs(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_CONSTANT_GS */
if (session->pcb_state_gs_changed)
p->gen6_3DSTATE_CONSTANT_GS(&p->gpe, NULL, NULL, 0, p->cp);
p->gen6_3DSTATE_CONSTANT_GS(p->dev, NULL, NULL, 0, p->cp);
/* 3DSTATE_GS */
if (DIRTY(GS) || DIRTY(VS) || session->prim_changed) {
@ -506,7 +506,7 @@ gen6_pipeline_gs(struct ilo_3d_pipeline *p,
if (gs)
assert(!gs->pcb.clip_state_size);
p->gen6_3DSTATE_GS(&p->gpe,
p->gen6_3DSTATE_GS(p->dev,
gs, ilo->max_gs_threads, vs,
(vs) ? vs->cache_offset + vs->gs_offsets[num_vertices - 1] : 0,
p->cp);
@ -548,10 +548,10 @@ gen6_pipeline_gs_svbi(struct ilo_3d_pipeline *p,
max_svbi = count;
}
if (p->gen == ILO_GEN(6))
if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
p->gen6_3DSTATE_GS_SVB_INDEX(&p->gpe,
p->gen6_3DSTATE_GS_SVB_INDEX(p->dev,
0, p->state.so_num_vertices, max_svbi,
false, p->cp);
@ -566,7 +566,7 @@ gen6_pipeline_gs_svbi(struct ilo_3d_pipeline *p,
* 0xFFFFFFFF in order to not cause overflow in that SVBI."
*/
for (i = 1; i < 4; i++) {
p->gen6_3DSTATE_GS_SVB_INDEX(&p->gpe,
p->gen6_3DSTATE_GS_SVB_INDEX(p->dev,
i, 0, 0xffffffff, false, p->cp);
}
}
@ -599,7 +599,7 @@ gen6_pipeline_clip(struct ilo_3d_pipeline *p,
(x1 <= 0.0f && x2 >= (float) ilo->framebuffer.width &&
y1 <= 0.0f && y2 >= (float) ilo->framebuffer.height);
p->gen6_3DSTATE_CLIP(&p->gpe,
p->gen6_3DSTATE_CLIP(p->dev,
ilo->rasterizer,
(ilo->fs && ilo->fs->shader->in.has_linear_interp),
enable_guardband, 1, p->cp);
@ -618,7 +618,7 @@ gen6_pipeline_sf(struct ilo_3d_pipeline *p,
(ilo->gs)? ilo->gs->shader :
(ilo->vs)? ilo->vs->shader : NULL;
p->gen6_3DSTATE_SF(&p->gpe,
p->gen6_3DSTATE_SF(p->dev,
ilo->rasterizer, fs, last_sh, p->cp);
}
}
@ -630,10 +630,10 @@ gen6_pipeline_sf_rect(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_DRAWING_RECTANGLE */
if (DIRTY(FRAMEBUFFER)) {
if (p->gen == ILO_GEN(6))
if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
p->gen6_3DSTATE_DRAWING_RECTANGLE(&p->gpe, 0, 0,
p->gen6_3DSTATE_DRAWING_RECTANGLE(p->dev, 0, 0,
ilo->framebuffer.width, ilo->framebuffer.height, p->cp);
}
}
@ -645,7 +645,7 @@ gen6_pipeline_wm(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_CONSTANT_PS */
if (session->pcb_state_fs_changed)
p->gen6_3DSTATE_CONSTANT_PS(&p->gpe, NULL, NULL, 0, p->cp);
p->gen6_3DSTATE_CONSTANT_PS(p->dev, NULL, NULL, 0, p->cp);
/* 3DSTATE_WM */
if (DIRTY(FS) || DIRTY(FRAGMENT_SAMPLERS) ||
@ -663,10 +663,10 @@ gen6_pipeline_wm(struct ilo_3d_pipeline *p,
if (fs)
assert(!fs->pcb.clip_state_size);
if (p->gen == ILO_GEN(6) && session->hw_ctx_changed)
if (p->dev->gen == ILO_GEN(6) && session->hw_ctx_changed)
gen6_wa_pipe_control_wm_max_threads_stall(p);
p->gen6_3DSTATE_WM(&p->gpe,
p->gen6_3DSTATE_WM(p->dev,
fs, ilo->max_wm_threads, num_samplers,
ilo->rasterizer, dual_blend, cc_may_kill, p->cp);
}
@ -688,15 +688,15 @@ gen6_pipeline_wm_multisample(struct ilo_3d_pipeline *p,
packed_sample_pos = (num_samples > 1) ?
&p->packed_sample_position_4x : &p->packed_sample_position_1x;
if (p->gen == ILO_GEN(6)) {
if (p->dev->gen == ILO_GEN(6)) {
gen6_wa_pipe_control_post_sync(p, false);
gen6_wa_pipe_control_wm_multisample_flush(p);
}
p->gen6_3DSTATE_MULTISAMPLE(&p->gpe, num_samples, packed_sample_pos,
p->gen6_3DSTATE_MULTISAMPLE(p->dev, num_samples, packed_sample_pos,
ilo->rasterizer->half_pixel_center, p->cp);
p->gen6_3DSTATE_SAMPLE_MASK(&p->gpe,
p->gen6_3DSTATE_SAMPLE_MASK(p->dev,
(num_samples > 1) ? ilo->sample_mask : 0x1, p->cp);
}
}
@ -708,16 +708,16 @@ gen6_pipeline_wm_depth(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
if (DIRTY(FRAMEBUFFER)) {
if (p->gen == ILO_GEN(6)) {
if (p->dev->gen == ILO_GEN(6)) {
gen6_wa_pipe_control_post_sync(p, false);
gen6_wa_pipe_control_wm_depth_flush(p);
}
p->gen6_3DSTATE_DEPTH_BUFFER(&p->gpe,
p->gen6_3DSTATE_DEPTH_BUFFER(p->dev,
ilo->framebuffer.zsbuf, false, p->cp);
/* TODO */
p->gen6_3DSTATE_CLEAR_PARAMS(&p->gpe, 0, p->cp);
p->gen6_3DSTATE_CLEAR_PARAMS(p->dev, 0, p->cp);
}
}
@ -729,31 +729,31 @@ gen6_pipeline_wm_raster(struct ilo_3d_pipeline *p,
/* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
if ((DIRTY(RASTERIZER) || DIRTY(POLY_STIPPLE)) &&
ilo->rasterizer->poly_stipple_enable) {
if (p->gen == ILO_GEN(6))
if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
p->gen6_3DSTATE_POLY_STIPPLE_PATTERN(&p->gpe,
p->gen6_3DSTATE_POLY_STIPPLE_PATTERN(p->dev,
&ilo->poly_stipple, p->cp);
p->gen6_3DSTATE_POLY_STIPPLE_OFFSET(&p->gpe, 0, 0, p->cp);
p->gen6_3DSTATE_POLY_STIPPLE_OFFSET(p->dev, 0, 0, p->cp);
}
/* 3DSTATE_LINE_STIPPLE */
if (DIRTY(RASTERIZER) && ilo->rasterizer->line_stipple_enable) {
if (p->gen == ILO_GEN(6))
if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
p->gen6_3DSTATE_LINE_STIPPLE(&p->gpe,
p->gen6_3DSTATE_LINE_STIPPLE(p->dev,
ilo->rasterizer->line_stipple_pattern,
ilo->rasterizer->line_stipple_factor + 1, p->cp);
}
/* 3DSTATE_AA_LINE_PARAMETERS */
if (DIRTY(RASTERIZER) && ilo->rasterizer->line_smooth) {
if (p->gen == ILO_GEN(6))
if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
p->gen6_3DSTATE_AA_LINE_PARAMETERS(&p->gpe, p->cp);
p->gen6_3DSTATE_AA_LINE_PARAMETERS(p->dev, p->cp);
}
}
@ -763,24 +763,24 @@ gen6_pipeline_state_viewports(struct ilo_3d_pipeline *p,
struct gen6_pipeline_session *session)
{
/* SF_CLIP_VIEWPORT and CC_VIEWPORT */
if (p->gen >= ILO_GEN(7) && DIRTY(VIEWPORT)) {
p->state.SF_CLIP_VIEWPORT = p->gen7_SF_CLIP_VIEWPORT(&p->gpe,
if (p->dev->gen >= ILO_GEN(7) && DIRTY(VIEWPORT)) {
p->state.SF_CLIP_VIEWPORT = p->gen7_SF_CLIP_VIEWPORT(p->dev,
&ilo->viewport, 1, p->cp);
p->state.CC_VIEWPORT = p->gen6_CC_VIEWPORT(&p->gpe,
p->state.CC_VIEWPORT = p->gen6_CC_VIEWPORT(p->dev,
&ilo->viewport, 1, p->cp);
session->viewport_state_changed = true;
}
/* SF_VIEWPORT, CLIP_VIEWPORT, and CC_VIEWPORT */
else if (DIRTY(VIEWPORT)) {
p->state.CLIP_VIEWPORT = p->gen6_CLIP_VIEWPORT(&p->gpe,
p->state.CLIP_VIEWPORT = p->gen6_CLIP_VIEWPORT(p->dev,
&ilo->viewport, 1, p->cp);
p->state.SF_VIEWPORT = p->gen6_SF_VIEWPORT(&p->gpe,
p->state.SF_VIEWPORT = p->gen6_SF_VIEWPORT(p->dev,
&ilo->viewport, 1, p->cp);
p->state.CC_VIEWPORT = p->gen6_CC_VIEWPORT(&p->gpe,
p->state.CC_VIEWPORT = p->gen6_CC_VIEWPORT(p->dev,
&ilo->viewport, 1, p->cp);
session->viewport_state_changed = true;
@ -794,7 +794,7 @@ gen6_pipeline_state_cc(struct ilo_3d_pipeline *p,
{
/* BLEND_STATE */
if (DIRTY(BLEND) || DIRTY(FRAMEBUFFER) || DIRTY(DEPTH_STENCIL_ALPHA)) {
p->state.BLEND_STATE = p->gen6_BLEND_STATE(&p->gpe,
p->state.BLEND_STATE = p->gen6_BLEND_STATE(p->dev,
ilo->blend, &ilo->framebuffer,
&ilo->depth_stencil_alpha->alpha, p->cp);
@ -803,7 +803,7 @@ gen6_pipeline_state_cc(struct ilo_3d_pipeline *p,
/* COLOR_CALC_STATE */
if (DIRTY(DEPTH_STENCIL_ALPHA) || DIRTY(STENCIL_REF) || DIRTY(BLEND_COLOR)) {
p->state.COLOR_CALC_STATE = p->gen6_COLOR_CALC_STATE(&p->gpe,
p->state.COLOR_CALC_STATE = p->gen6_COLOR_CALC_STATE(p->dev,
&ilo->stencil_ref,
ilo->depth_stencil_alpha->alpha.ref_value,
&ilo->blend_color, p->cp);
@ -814,7 +814,7 @@ gen6_pipeline_state_cc(struct ilo_3d_pipeline *p,
/* DEPTH_STENCIL_STATE */
if (DIRTY(DEPTH_STENCIL_ALPHA)) {
p->state.DEPTH_STENCIL_STATE =
p->gen6_DEPTH_STENCIL_STATE(&p->gpe,
p->gen6_DEPTH_STENCIL_STATE(p->dev,
ilo->depth_stencil_alpha, p->cp);
session->cc_state_dsa_changed = true;
@ -828,7 +828,7 @@ gen6_pipeline_state_scissors(struct ilo_3d_pipeline *p,
{
/* SCISSOR_RECT */
if (DIRTY(SCISSOR)) {
p->state.SCISSOR_RECT = p->gen6_SCISSOR_RECT(&p->gpe,
p->state.SCISSOR_RECT = p->gen6_SCISSOR_RECT(p->dev,
&ilo->scissor, 1, p->cp);
session->scissor_state_changed = true;
@ -851,7 +851,7 @@ gen6_pipeline_state_surfaces_rt(struct ilo_3d_pipeline *p,
assert(surface);
surface_state[i] =
p->gen6_surf_SURFACE_STATE(&p->gpe, surface, p->cp);
p->gen6_surf_SURFACE_STATE(p->dev, surface, p->cp);
}
/*
@ -866,7 +866,7 @@ gen6_pipeline_state_surfaces_rt(struct ilo_3d_pipeline *p,
null_surface.height = ilo->framebuffer.height;
surface_state[i] =
p->gen6_surf_SURFACE_STATE(&p->gpe, &null_surface, p->cp);
p->gen6_surf_SURFACE_STATE(p->dev, &null_surface, p->cp);
i++;
}
@ -892,7 +892,7 @@ gen6_pipeline_state_surfaces_so(struct ilo_3d_pipeline *p,
ilo->stream_output_targets.targets;
const int num_so_targets = ilo->stream_output_targets.num_targets;
if (p->gen != ILO_GEN(6))
if (p->dev->gen != ILO_GEN(6))
return;
/* SURFACE_STATEs for stream output targets */
@ -910,7 +910,7 @@ gen6_pipeline_state_surfaces_so(struct ilo_3d_pipeline *p,
(target < num_so_targets) ? so_targets[target] : NULL;
if (so_target) {
surface_state[i] = p->gen6_so_SURFACE_STATE(&p->gpe,
surface_state[i] = p->gen6_so_SURFACE_STATE(p->dev,
so_target, so_info, i, p->cp);
}
else {
@ -976,7 +976,7 @@ gen6_pipeline_state_surfaces_view(struct ilo_3d_pipeline *p,
for (i = 0; i < num_views; i++) {
if (views[i]) {
surface_state[i] =
p->gen6_view_SURFACE_STATE(&p->gpe, views[i], p->cp);
p->gen6_view_SURFACE_STATE(p->dev, views[i], p->cp);
}
else {
surface_state[i] = 0;
@ -1037,7 +1037,7 @@ gen6_pipeline_state_surfaces_const(struct ilo_3d_pipeline *p,
for (i = 0; i < num_buffers; i++) {
if (buffers[i].buffer) {
surface_state[i] =
p->gen6_cbuf_SURFACE_STATE(&p->gpe, &buffers[i], p->cp);
p->gen6_cbuf_SURFACE_STATE(p->dev, &buffers[i], p->cp);
}
else {
surface_state[i] = 0;
@ -1104,7 +1104,7 @@ gen6_pipeline_state_binding_tables(struct ilo_3d_pipeline *p,
if (size < session->num_surfaces[shader_type])
size = session->num_surfaces[shader_type];
*binding_table_state = p->gen6_BINDING_TABLE_STATE(&p->gpe,
*binding_table_state = p->gen6_BINDING_TABLE_STATE(p->dev,
surface_state, size, p->cp);
*binding_table_state_size = size;
}
@ -1170,13 +1170,13 @@ gen6_pipeline_state_samplers(struct ilo_3d_pipeline *p,
for (i = 0; i < num_samplers; i++) {
border_color_state[i] = (samplers[i]) ?
p->gen6_SAMPLER_BORDER_COLOR_STATE(&p->gpe,
p->gen6_SAMPLER_BORDER_COLOR_STATE(p->dev,
&samplers[i]->border_color, p->cp) : 0;
}
}
/* should we take the minimum of num_samplers and num_views? */
*sampler_state = p->gen6_SAMPLER_STATE(&p->gpe,
*sampler_state = p->gen6_SAMPLER_STATE(p->dev,
samplers, views,
border_color_state,
MIN2(num_samplers, num_views), p->cp);
@ -1196,7 +1196,7 @@ gen6_pipeline_state_pcb(struct ilo_3d_pipeline *p,
p->state.vs.PUSH_CONSTANT_BUFFER_size = vs->pcb.clip_state_size;
p->state.vs.PUSH_CONSTANT_BUFFER =
p->gen6_push_constant_buffer(&p->gpe,
p->gen6_push_constant_buffer(p->dev,
p->state.vs.PUSH_CONSTANT_BUFFER_size, &pcb, p->cp);
memcpy(pcb, &ilo->clip, vs->pcb.clip_state_size);
@ -1362,10 +1362,10 @@ ilo_3d_pipeline_emit_draw_gen6(struct ilo_3d_pipeline *p,
void
ilo_3d_pipeline_emit_flush_gen6(struct ilo_3d_pipeline *p)
{
if (p->gen == ILO_GEN(6))
if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_INSTRUCTION_FLUSH |
PIPE_CONTROL_WRITE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
@ -1380,10 +1380,10 @@ void
ilo_3d_pipeline_emit_write_timestamp_gen6(struct ilo_3d_pipeline *p,
struct intel_bo *bo, int index)
{
if (p->gen == ILO_GEN(6))
if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, true);
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_WRITE_TIMESTAMP,
bo, index * sizeof(uint64_t) | PIPE_CONTROL_GLOBAL_GTT_WRITE,
true, p->cp);
@ -1393,10 +1393,10 @@ void
ilo_3d_pipeline_emit_write_depth_count_gen6(struct ilo_3d_pipeline *p,
struct intel_bo *bo, int index)
{
if (p->gen == ILO_GEN(6))
if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_WRITE_DEPTH_COUNT,
bo, index * sizeof(uint64_t) | PIPE_CONTROL_GLOBAL_GTT_WRITE,
@ -1451,7 +1451,7 @@ gen6_pipeline_estimate_commands(const struct ilo_3d_pipeline *p,
}
if (count)
size += gen6->estimate_command_size(&p->gpe, cmd, count);
size += gen6->estimate_command_size(p->dev, cmd, count);
}
return size;
@ -1488,7 +1488,7 @@ gen6_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
int i;
for (i = 0; i < Elements(static_states); i++) {
static_size += gen6->estimate_state_size(&p->gpe,
static_size += gen6->estimate_state_size(p->dev,
static_states[i].state,
static_states[i].count);
}
@ -1515,7 +1515,7 @@ gen6_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
}
if (count) {
size += gen6->estimate_state_size(&p->gpe,
size += gen6->estimate_state_size(p->dev,
ILO_GPE_GEN6_SURFACE_STATE, count);
}
@ -1523,9 +1523,9 @@ gen6_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
count = ilo->samplers[shader_type].num_samplers;
if (count) {
size += gen6->estimate_state_size(&p->gpe,
size += gen6->estimate_state_size(p->dev,
ILO_GPE_GEN6_SAMPLER_BORDER_COLOR_STATE, count);
size += gen6->estimate_state_size(&p->gpe,
size += gen6->estimate_state_size(p->dev,
ILO_GPE_GEN6_SAMPLER_STATE, count);
}
}
@ -1534,7 +1534,7 @@ gen6_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
if (ilo->vs && ilo->vs->shader->pcb.clip_state_size) {
const int pcb_size = ilo->vs->shader->pcb.clip_state_size;
size += gen6->estimate_state_size(&p->gpe,
size += gen6->estimate_state_size(p->dev,
ILO_GPE_GEN6_PUSH_CONSTANT_BUFFER, pcb_size);
}
@ -1559,15 +1559,15 @@ ilo_3d_pipeline_estimate_size_gen6(struct ilo_3d_pipeline *p,
}
break;
case ILO_3D_PIPELINE_FLUSH:
size = gen6->estimate_command_size(&p->gpe,
size = gen6->estimate_command_size(p->dev,
ILO_GPE_GEN6_PIPE_CONTROL, 1) * 3;
break;
case ILO_3D_PIPELINE_WRITE_TIMESTAMP:
size = gen6->estimate_command_size(&p->gpe,
size = gen6->estimate_command_size(p->dev,
ILO_GPE_GEN6_PIPE_CONTROL, 1) * 2;
break;
case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT:
size = gen6->estimate_command_size(&p->gpe,
size = gen6->estimate_command_size(p->dev,
ILO_GPE_GEN6_PIPE_CONTROL, 1) * 3;
break;
default:

112
src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c
View file

@ -46,7 +46,7 @@ gen7_wa_pipe_control_cs_stall(struct ilo_3d_pipeline *p,
struct intel_bo *bo = NULL;
uint32_t dw1 = PIPE_CONTROL_CS_STALL;
assert(p->gen == ILO_GEN(7));
assert(p->dev->gen == ILO_GEN(7));
/* emit once */
if (p->state.has_gen6_wa_pipe_control)
@ -88,13 +88,13 @@ gen7_wa_pipe_control_cs_stall(struct ilo_3d_pipeline *p,
bo = p->workaround_bo;
}
p->gen6_PIPE_CONTROL(&p->gpe, dw1, bo, 0, false, p->cp);
p->gen6_PIPE_CONTROL(p->dev, dw1, bo, 0, false, p->cp);
}
static void
gen7_wa_pipe_control_vs_depth_stall(struct ilo_3d_pipeline *p)
{
assert(p->gen == ILO_GEN(7));
assert(p->dev->gen == ILO_GEN(7));
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 106:
@ -105,7 +105,7 @@ gen7_wa_pipe_control_vs_depth_stall(struct ilo_3d_pipeline *p)
* 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
* needs to be sent before any combination of VS associated 3DSTATE."
*/
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_WRITE_IMMEDIATE,
p->workaround_bo, 0, false, p->cp);
@ -115,7 +115,7 @@ static void
gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline *p,
bool change_depth_buffer)
{
assert(p->gen == ILO_GEN(7));
assert(p->dev->gen == ILO_GEN(7));
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 276:
@ -144,18 +144,18 @@ gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline *p,
* guarantee that the pipeline from WM onwards is already flushed
* (e.g., via a preceding MI_FLUSH)."
*/
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL,
NULL, 0, false, p->cp);
if (!change_depth_buffer)
return;
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_CACHE_FLUSH,
NULL, 0, false, p->cp);
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL,
NULL, 0, false, p->cp);
}
@ -163,7 +163,7 @@ gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline *p,
static void
gen7_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
{
assert(p->gen == ILO_GEN(7));
assert(p->dev->gen == ILO_GEN(7));
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 286:
@ -172,7 +172,7 @@ gen7_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
* between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
* Pixel Scoreboard set is required to be issued."
*/
p->gen6_PIPE_CONTROL(&p->gpe,
p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_STALL_AT_SCOREBOARD,
NULL, 0, false, p->cp);
@ -210,12 +210,12 @@ gen7_pipeline_common_urb(struct ilo_3d_pipeline *p,
gen7_wa_pipe_control_vs_depth_stall(p);
p->gen7_3DSTATE_URB_VS(&p->gpe,
p->gen7_3DSTATE_URB_VS(p->dev,
offset, vs_total_size, vs_entry_size, p->cp);
p->gen7_3DSTATE_URB_GS(&p->gpe, offset, 0, 0, p->cp);
p->gen7_3DSTATE_URB_HS(&p->gpe, offset, 0, 0, p->cp);
p->gen7_3DSTATE_URB_DS(&p->gpe, offset, 0, 0, p->cp);
p->gen7_3DSTATE_URB_GS(p->dev, offset, 0, 0, p->cp);
p->gen7_3DSTATE_URB_HS(p->dev, offset, 0, 0, p->cp);
p->gen7_3DSTATE_URB_DS(p->dev, offset, 0, 0, p->cp);
}
}
@ -230,10 +230,10 @@ gen7_pipeline_common_pcb_alloc(struct ilo_3d_pipeline *p,
* push constant buffers are only allowed to take up at most the first
* 16KB of the URB
*/
p->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(&p->gpe,
p->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(p->dev,
0, 8192, p->cp);
p->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(&p->gpe,
p->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(p->dev,
8192, 8192, p->cp);
gen7_wa_pipe_control_cs_stall(p, true, true);
@ -247,10 +247,10 @@ gen7_pipeline_common_pointers_1(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
if (session->viewport_state_changed) {
p->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(&p->gpe,
p->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(p->dev,
p->state.CC_VIEWPORT, p->cp);
p->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(&p->gpe,
p->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(p->dev,
p->state.SF_CLIP_VIEWPORT, p->cp);
}
}
@ -262,19 +262,19 @@ gen7_pipeline_common_pointers_2(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_BLEND_STATE_POINTERS */
if (session->cc_state_blend_changed) {
p->gen7_3DSTATE_BLEND_STATE_POINTERS(&p->gpe,
p->gen7_3DSTATE_BLEND_STATE_POINTERS(p->dev,
p->state.BLEND_STATE, p->cp);
}
/* 3DSTATE_CC_STATE_POINTERS */
if (session->cc_state_cc_changed) {
p->gen7_3DSTATE_CC_STATE_POINTERS(&p->gpe,
p->gen7_3DSTATE_CC_STATE_POINTERS(p->dev,
p->state.COLOR_CALC_STATE, p->cp);
}
/* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
if (session->cc_state_dsa_changed) {
p->gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(&p->gpe,
p->gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(p->dev,
p->state.DEPTH_STENCIL_STATE, p->cp);
}
}
@ -297,13 +297,13 @@ gen7_pipeline_vs(struct ilo_3d_pipeline *p,
/* 3DSTATE_BINDING_TABLE_POINTERS_VS */
if (emit_3dstate_binding_table) {
p->gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(&p->gpe,
p->gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(p->dev,
p->state.vs.BINDING_TABLE_STATE, p->cp);
}
/* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
if (emit_3dstate_sampler_state) {
p->gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(&p->gpe,
p->gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(p->dev,
p->state.vs.SAMPLER_STATE, p->cp);
}
@ -317,13 +317,13 @@ gen7_pipeline_hs(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
if (session->hw_ctx_changed) {
p->gen7_3DSTATE_CONSTANT_HS(&p->gpe, 0, 0, 0, p->cp);
p->gen7_3DSTATE_HS(&p->gpe, NULL, 0, 0, p->cp);
p->gen7_3DSTATE_CONSTANT_HS(p->dev, 0, 0, 0, p->cp);
p->gen7_3DSTATE_HS(p->dev, NULL, 0, 0, p->cp);
}
/* 3DSTATE_BINDING_TABLE_POINTERS_HS */
if (session->hw_ctx_changed)
p->gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(&p->gpe, 0, p->cp);
p->gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(p->dev, 0, p->cp);
}
static void
@ -333,7 +333,7 @@ gen7_pipeline_te(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_TE */
if (session->hw_ctx_changed)
p->gen7_3DSTATE_TE(&p->gpe, p->cp);
p->gen7_3DSTATE_TE(p->dev, p->cp);
}
static void
@ -343,13 +343,13 @@ gen7_pipeline_ds(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
if (session->hw_ctx_changed) {
p->gen7_3DSTATE_CONSTANT_DS(&p->gpe, 0, 0, 0, p->cp);
p->gen7_3DSTATE_DS(&p->gpe, NULL, 0, 0, p->cp);
p->gen7_3DSTATE_CONSTANT_DS(p->dev, 0, 0, 0, p->cp);
p->gen7_3DSTATE_DS(p->dev, NULL, 0, 0, p->cp);
}
/* 3DSTATE_BINDING_TABLE_POINTERS_DS */
if (session->hw_ctx_changed)
p->gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(&p->gpe, 0, p->cp);
p->gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(p->dev, 0, p->cp);
}
@ -360,13 +360,13 @@ gen7_pipeline_gs(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
if (session->hw_ctx_changed) {
p->gen6_3DSTATE_CONSTANT_GS(&p->gpe, 0, 0, 0, p->cp);
p->gen7_3DSTATE_GS(&p->gpe, NULL, 0, 0, p->cp);
p->gen6_3DSTATE_CONSTANT_GS(p->dev, 0, 0, 0, p->cp);
p->gen7_3DSTATE_GS(p->dev, NULL, 0, 0, p->cp);
}
/* 3DSTATE_BINDING_TABLE_POINTERS_GS */
if (session->binding_table_gs_changed) {
p->gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(&p->gpe,
p->gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(p->dev,
p->state.gs.BINDING_TABLE_STATE, p->cp);
}
}
@ -381,12 +381,12 @@ gen7_pipeline_sol(struct ilo_3d_pipeline *p,
int i;
for (i = 0; i < 4; i++)
p->gen7_3DSTATE_SO_BUFFER(&p->gpe, i, false, p->cp);
p->gen7_3DSTATE_SO_BUFFER(p->dev, i, false, p->cp);
p->gen7_3DSTATE_SO_DECL_LIST(&p->gpe, p->cp);
p->gen7_3DSTATE_SO_DECL_LIST(p->dev, p->cp);
}
p->gen7_3DSTATE_STREAMOUT(&p->gpe, false, false, false, p->cp);
p->gen7_3DSTATE_STREAMOUT(p->dev, false, false, false, p->cp);
}
}
@ -402,7 +402,7 @@ gen7_pipeline_sf(struct ilo_3d_pipeline *p,
(ilo->gs)? ilo->gs->shader :
(ilo->vs)? ilo->vs->shader : NULL;
p->gen7_3DSTATE_SBE(&p->gpe,
p->gen7_3DSTATE_SBE(p->dev,
ilo->rasterizer, fs, last_sh, p->cp);
}
@ -410,7 +410,7 @@ gen7_pipeline_sf(struct ilo_3d_pipeline *p,
if (DIRTY(RASTERIZER) || DIRTY(FRAMEBUFFER)) {
gen7_wa_pipe_control_cs_stall(p, true, true);
p->gen7_3DSTATE_SF(&p->gpe,
p->gen7_3DSTATE_SF(p->dev,
ilo->rasterizer, ilo->framebuffer.zsbuf, p->cp);
}
}
@ -430,28 +430,28 @@ gen7_pipeline_wm(struct ilo_3d_pipeline *p,
if (fs)
assert(!fs->pcb.clip_state_size);
if (p->gen == ILO_GEN(7) && session->hw_ctx_changed)
if (p->dev->gen == ILO_GEN(7) && session->hw_ctx_changed)
gen7_wa_pipe_control_wm_max_threads_stall(p);
p->gen7_3DSTATE_WM(&p->gpe,
p->gen7_3DSTATE_WM(p->dev,
fs, ilo->rasterizer, cc_may_kill, p->cp);
}
/* 3DSTATE_BINDING_TABLE_POINTERS_PS */
if (session->binding_table_fs_changed) {
p->gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(&p->gpe,
p->gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(p->dev,
p->state.wm.BINDING_TABLE_STATE, p->cp);
}
/* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
if (session->sampler_state_fs_changed) {
p->gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(&p->gpe,
p->gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(p->dev,
p->state.wm.SAMPLER_STATE, p->cp);
}
/* 3DSTATE_CONSTANT_PS */
if (session->pcb_state_fs_changed)
p->gen6_3DSTATE_CONSTANT_PS(&p->gpe, NULL, NULL, 0, p->cp);
p->gen6_3DSTATE_CONSTANT_PS(p->dev, NULL, NULL, 0, p->cp);
/* 3DSTATE_PS */
if (DIRTY(FS) || DIRTY(FRAGMENT_SAMPLERS) ||
@ -466,14 +466,14 @@ gen7_pipeline_wm(struct ilo_3d_pipeline *p,
if (fs)
assert(!fs->pcb.clip_state_size);
p->gen7_3DSTATE_PS(&p->gpe,
p->gen7_3DSTATE_PS(p->dev,
fs, ilo->max_wm_threads, num_samplers,
dual_blend, p->cp);
}
/* 3DSTATE_SCISSOR_STATE_POINTERS */
if (session->scissor_state_changed) {
p->gen6_3DSTATE_SCISSOR_STATE_POINTERS(&p->gpe,
p->gen6_3DSTATE_SCISSOR_STATE_POINTERS(p->dev,
p->state.SCISSOR_RECT, p->cp);
}
@ -508,13 +508,13 @@ gen7_pipeline_wm(struct ilo_3d_pipeline *p,
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
if (DIRTY(FRAMEBUFFER) || DIRTY(DEPTH_STENCIL_ALPHA) ||
session->state_bo_changed) {
p->gen7_3DSTATE_DEPTH_BUFFER(&p->gpe,
p->gen7_3DSTATE_DEPTH_BUFFER(p->dev,
ilo->framebuffer.zsbuf,
ilo->depth_stencil_alpha,
false, p->cp);
/* TODO */
p->gen6_3DSTATE_CLEAR_PARAMS(&p->gpe, 0, p->cp);
p->gen6_3DSTATE_CLEAR_PARAMS(p->dev, 0, p->cp);
}
}
@ -538,10 +538,10 @@ gen7_pipeline_wm_multisample(struct ilo_3d_pipeline *p,
(num_samples > 1) ? &p->packed_sample_position_4x :
&p->packed_sample_position_1x;
p->gen6_3DSTATE_MULTISAMPLE(&p->gpe, num_samples, packed_sample_pos,
p->gen6_3DSTATE_MULTISAMPLE(p->dev, num_samples, packed_sample_pos,
ilo->rasterizer->half_pixel_center, p->cp);
p->gen7_3DSTATE_SAMPLE_MASK(&p->gpe,
p->gen7_3DSTATE_SAMPLE_MASK(p->dev,
(num_samples > 1) ? ilo->sample_mask : 0x1,
num_samples, p->cp);
}
@ -640,7 +640,7 @@ gen7_pipeline_estimate_commands(const struct ilo_3d_pipeline *p,
}
if (count) {
size += gen7->estimate_command_size(&p->gpe,
size += gen7->estimate_command_size(p->dev,
cmd, count);
}
}
@ -678,7 +678,7 @@ gen7_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
int i;
for (i = 0; i < Elements(static_states); i++) {
static_size += gen7->estimate_state_size(&p->gpe,
static_size += gen7->estimate_state_size(p->dev,
static_states[i].state,
static_states[i].count);
}
@ -698,7 +698,7 @@ gen7_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
}
if (count) {
size += gen7->estimate_state_size(&p->gpe,
size += gen7->estimate_state_size(p->dev,
ILO_GPE_GEN7_SURFACE_STATE, count);
}
@ -706,9 +706,9 @@ gen7_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
count = ilo->samplers[shader_type].num_samplers;
if (count) {
size += gen7->estimate_state_size(&p->gpe,
size += gen7->estimate_state_size(p->dev,
ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE, count);
size += gen7->estimate_state_size(&p->gpe,
size += gen7->estimate_state_size(p->dev,
ILO_GPE_GEN7_SAMPLER_STATE, count);
}
}
@ -717,7 +717,7 @@ gen7_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
if (ilo->vs && ilo->vs->shader->pcb.clip_state_size) {
const int pcb_size = ilo->vs->shader->pcb.clip_state_size;
size += gen7->estimate_state_size(&p->gpe,
size += gen7->estimate_state_size(p->dev,
ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER, pcb_size);
}
@ -744,7 +744,7 @@ ilo_3d_pipeline_estimate_size_gen7(struct ilo_3d_pipeline *p,
case ILO_3D_PIPELINE_FLUSH:
case ILO_3D_PIPELINE_WRITE_TIMESTAMP:
case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT:
size = gen7->estimate_command_size(&p->gpe,
size = gen7->estimate_command_size(p->dev,
ILO_GPE_GEN7_PIPE_CONTROL, 1);
break;
default:

2
src/gallium/drivers/ilo/ilo_context.c
View file

@ -178,7 +178,7 @@ ilo_context_create(struct pipe_screen *screen, void *priv)
ilo->cp = ilo_cp_create(ilo->winsys, is->dev.has_llc);
ilo->shader_cache = ilo_shader_cache_create(ilo->winsys);
if (ilo->cp)
ilo->hw3d = ilo_3d_create(ilo->cp, ilo->dev->gen, ilo->dev->gt);
ilo->hw3d = ilo_3d_create(ilo->cp, ilo->dev);
if (!ilo->cp || !ilo->shader_cache || !ilo->hw3d) {
ilo_context_destroy(&ilo->base);

366
src/gallium/drivers/ilo/ilo_gpe_gen6.c
View file

File diff suppressed because it is too large Load diff

137
src/gallium/drivers/ilo/ilo_gpe_gen6.h
View file

@ -30,17 +30,12 @@
#include "ilo_common.h"
#define ILO_GPE_VALID_GEN(gpe, min_gen, max_gen) \
assert((gpe)->gen >= ILO_GEN(min_gen) && (gpe)->gen <= ILO_GEN(max_gen))
#define ILO_GPE_VALID_GEN(dev, min_gen, max_gen) \
assert((dev)->gen >= ILO_GEN(min_gen) && (dev)->gen <= ILO_GEN(max_gen))
#define ILO_GPE_CMD(pipeline, op, subop) \
(0x3 << 29 | (pipeline) << 27 | (op) << 24 | (subop) << 16)
struct ilo_gpe {
int gen;
int gt;
};
/**
* Commands that GEN6 GPE could emit.
*/
@ -119,7 +114,7 @@ struct ilo_resource;
struct ilo_shader;
typedef void
(*ilo_gpe_gen6_STATE_BASE_ADDRESS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_STATE_BASE_ADDRESS)(const struct ilo_dev_info *dev,
struct intel_bo *general_state_bo,
struct intel_bo *surface_state_bo,
struct intel_bo *dynamic_state_bo,
@ -132,80 +127,80 @@ typedef void
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_STATE_SIP)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_STATE_SIP)(const struct ilo_dev_info *dev,
uint32_t sip,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_VF_STATISTICS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_VF_STATISTICS)(const struct ilo_dev_info *dev,
bool enable,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_PIPELINE_SELECT)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_PIPELINE_SELECT)(const struct ilo_dev_info *dev,
int pipeline,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_MEDIA_VFE_STATE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_MEDIA_VFE_STATE)(const struct ilo_dev_info *dev,
int max_threads, int num_urb_entries,
int urb_entry_size,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_MEDIA_CURBE_LOAD)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_MEDIA_CURBE_LOAD)(const struct ilo_dev_info *dev,
uint32_t buf, int size,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_MEDIA_INTERFACE_DESCRIPTOR_LOAD)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_MEDIA_INTERFACE_DESCRIPTOR_LOAD)(const struct ilo_dev_info *dev,
uint32_t offset, int num_ids,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_MEDIA_GATEWAY_STATE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_MEDIA_GATEWAY_STATE)(const struct ilo_dev_info *dev,
int id, int byte, int thread_count,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_MEDIA_STATE_FLUSH)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_MEDIA_STATE_FLUSH)(const struct ilo_dev_info *dev,
int thread_count_water_mark,
int barrier_mask,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_MEDIA_OBJECT_WALKER)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_MEDIA_OBJECT_WALKER)(const struct ilo_dev_info *dev,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_BINDING_TABLE_POINTERS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_BINDING_TABLE_POINTERS)(const struct ilo_dev_info *dev,
uint32_t vs_binding_table,
uint32_t gs_binding_table,
uint32_t ps_binding_table,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_SAMPLER_STATE_POINTERS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_SAMPLER_STATE_POINTERS)(const struct ilo_dev_info *dev,
uint32_t vs_sampler_state,
uint32_t gs_sampler_state,
uint32_t ps_sampler_state,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_URB)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_URB)(const struct ilo_dev_info *dev,
int vs_total_size, int gs_total_size,
int vs_entry_size, int gs_entry_size,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_VERTEX_BUFFERS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_VERTEX_BUFFERS)(const struct ilo_dev_info *dev,
const struct pipe_vertex_buffer *vbuffers,
const int *instance_divisors,
uint32_t vbuffer_mask,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_VERTEX_ELEMENTS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_VERTEX_ELEMENTS)(const struct ilo_dev_info *dev,
const struct pipe_vertex_element *velements,
int num_elements,
bool last_velement_edgeflag,
@ -213,46 +208,46 @@ typedef void
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_INDEX_BUFFER)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_INDEX_BUFFER)(const struct ilo_dev_info *dev,
const struct pipe_index_buffer *ib,
bool enable_cut_index,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_VIEWPORT_STATE_POINTERS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_VIEWPORT_STATE_POINTERS)(const struct ilo_dev_info *dev,
uint32_t clip_viewport,
uint32_t sf_viewport,
uint32_t cc_viewport,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_CC_STATE_POINTERS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_CC_STATE_POINTERS)(const struct ilo_dev_info *dev,
uint32_t blend_state,
uint32_t depth_stencil_state,
uint32_t color_calc_state,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_SCISSOR_STATE_POINTERS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_SCISSOR_STATE_POINTERS)(const struct ilo_dev_info *dev,
uint32_t scissor_rect,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_VS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_VS)(const struct ilo_dev_info *dev,
const struct ilo_shader *vs,
int max_threads, int num_samplers,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_GS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_GS)(const struct ilo_dev_info *dev,
const struct ilo_shader *gs,
int max_threads, const struct ilo_shader *vs,
uint32_t vs_offset,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_CLIP)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_CLIP)(const struct ilo_dev_info *dev,
const struct pipe_rasterizer_state *rasterizer,
bool has_linear_interp,
bool enable_guardband,
@ -260,14 +255,14 @@ typedef void
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_SF)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_SF)(const struct ilo_dev_info *dev,
const struct pipe_rasterizer_state *rasterizer,
const struct ilo_shader *fs,
const struct ilo_shader *last_sh,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_WM)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_WM)(const struct ilo_dev_info *dev,
const struct ilo_shader *fs,
int max_threads, int num_samplers,
const struct pipe_rasterizer_state *rasterizer,
@ -275,61 +270,61 @@ typedef void
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_CONSTANT_VS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_CONSTANT_VS)(const struct ilo_dev_info *dev,
const uint32_t *bufs, const int *sizes,
int num_bufs,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_CONSTANT_GS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_CONSTANT_GS)(const struct ilo_dev_info *dev,
const uint32_t *bufs, const int *sizes,
int num_bufs,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_CONSTANT_PS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_CONSTANT_PS)(const struct ilo_dev_info *dev,
const uint32_t *bufs, const int *sizes,
int num_bufs,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_SAMPLE_MASK)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_SAMPLE_MASK)(const struct ilo_dev_info *dev,
unsigned sample_mask,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_DRAWING_RECTANGLE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_DRAWING_RECTANGLE)(const struct ilo_dev_info *dev,
unsigned x, unsigned y,
unsigned width, unsigned height,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_DEPTH_BUFFER)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_DEPTH_BUFFER)(const struct ilo_dev_info *dev,
const struct pipe_surface *surface,
bool hiz,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_POLY_STIPPLE_OFFSET)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_POLY_STIPPLE_OFFSET)(const struct ilo_dev_info *dev,
int x_offset, int y_offset,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_POLY_STIPPLE_PATTERN)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_POLY_STIPPLE_PATTERN)(const struct ilo_dev_info *dev,
const struct pipe_poly_stipple *pattern,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_LINE_STIPPLE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_LINE_STIPPLE)(const struct ilo_dev_info *dev,
unsigned pattern, unsigned factor,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_AA_LINE_PARAMETERS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_AA_LINE_PARAMETERS)(const struct ilo_dev_info *dev,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_GS_SVB_INDEX)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_GS_SVB_INDEX)(const struct ilo_dev_info *dev,
int index, unsigned svbi,
unsigned max_svbi,
bool load_vertex_count,
@ -337,42 +332,42 @@ typedef void
typedef void
(*ilo_gpe_gen6_3DSTATE_MULTISAMPLE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_MULTISAMPLE)(const struct ilo_dev_info *dev,
int num_samples,
const uint32_t *packed_sample_pos,
bool pixel_location_center,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_STENCIL_BUFFER)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_STENCIL_BUFFER)(const struct ilo_dev_info *dev,
const struct pipe_surface *surface,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_HIER_DEPTH_BUFFER)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_HIER_DEPTH_BUFFER)(const struct ilo_dev_info *dev,
const struct pipe_surface *surface,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DSTATE_CLEAR_PARAMS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DSTATE_CLEAR_PARAMS)(const struct ilo_dev_info *dev,
uint32_t clear_val,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_PIPE_CONTROL)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_PIPE_CONTROL)(const struct ilo_dev_info *dev,
uint32_t dw1,
struct intel_bo *bo, uint32_t bo_offset,
bool write_qword,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen6_3DPRIMITIVE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_3DPRIMITIVE)(const struct ilo_dev_info *dev,
const struct pipe_draw_info *info,
bool rectlist,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_INTERFACE_DESCRIPTOR_DATA)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_INTERFACE_DESCRIPTOR_DATA)(const struct ilo_dev_info *dev,
const struct ilo_shader **cs,
uint32_t *sampler_state,
int *num_samplers,
@ -381,78 +376,78 @@ typedef uint32_t
int num_ids,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_SF_VIEWPORT)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_SF_VIEWPORT)(const struct ilo_dev_info *dev,
const struct pipe_viewport_state *viewports,
int num_viewports,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_CLIP_VIEWPORT)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_CLIP_VIEWPORT)(const struct ilo_dev_info *dev,
const struct pipe_viewport_state *viewports,
int num_viewports,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_CC_VIEWPORT)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_CC_VIEWPORT)(const struct ilo_dev_info *dev,
const struct pipe_viewport_state *viewports,
int num_viewports,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_COLOR_CALC_STATE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_COLOR_CALC_STATE)(const struct ilo_dev_info *dev,
const struct pipe_stencil_ref *stencil_ref,
float alpha_ref,
const struct pipe_blend_color *blend_color,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_BLEND_STATE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_BLEND_STATE)(const struct ilo_dev_info *dev,
const struct pipe_blend_state *blend,
const struct pipe_framebuffer_state *framebuffer,
const struct pipe_alpha_state *alpha,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_DEPTH_STENCIL_STATE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_DEPTH_STENCIL_STATE)(const struct ilo_dev_info *dev,
const struct pipe_depth_stencil_alpha_state *dsa,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_SCISSOR_RECT)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_SCISSOR_RECT)(const struct ilo_dev_info *dev,
const struct pipe_scissor_state *scissors,
int num_scissors,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_BINDING_TABLE_STATE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_BINDING_TABLE_STATE)(const struct ilo_dev_info *dev,
uint32_t *surface_states,
int num_surface_states,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_surf_SURFACE_STATE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_surf_SURFACE_STATE)(const struct ilo_dev_info *dev,
const struct pipe_surface *surface,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_view_SURFACE_STATE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_view_SURFACE_STATE)(const struct ilo_dev_info *dev,
const struct pipe_sampler_view *view,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_cbuf_SURFACE_STATE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_cbuf_SURFACE_STATE)(const struct ilo_dev_info *dev,
const struct pipe_constant_buffer *cbuf,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_so_SURFACE_STATE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_so_SURFACE_STATE)(const struct ilo_dev_info *dev,
const struct pipe_stream_output_target *so,
const struct pipe_stream_output_info *so_info,
int so_index,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_SAMPLER_STATE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_SAMPLER_STATE)(const struct ilo_dev_info *dev,
const struct pipe_sampler_state **samplers,
const struct pipe_sampler_view **sampler_views,
const uint32_t *sampler_border_colors,
@ -460,12 +455,12 @@ typedef uint32_t
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_SAMPLER_BORDER_COLOR_STATE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_SAMPLER_BORDER_COLOR_STATE)(const struct ilo_dev_info *dev,
const union pipe_color_union *color,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_push_constant_buffer)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen6_push_constant_buffer)(const struct ilo_dev_info *dev,
int size, void **pcb,
struct ilo_cp *cp);
@ -476,11 +471,11 @@ typedef uint32_t
* between states.
*/
struct ilo_gpe_gen6 {
int (*estimate_command_size)(const struct ilo_gpe *gpe,
int (*estimate_command_size)(const struct ilo_dev_info *dev,
enum ilo_gpe_gen6_command cmd,
int arg);
int (*estimate_state_size)(const struct ilo_gpe *gpe,
int (*estimate_state_size)(const struct ilo_dev_info *dev,
enum ilo_gpe_gen6_state state,
int arg);
@ -560,7 +555,7 @@ int
ilo_gpe_gen6_translate_texture(enum pipe_texture_target target);
void
ilo_gpe_gen6_fill_3dstate_sf_raster(const struct ilo_gpe *gpe,
ilo_gpe_gen6_fill_3dstate_sf_raster(const struct ilo_dev_info *dev,
const struct pipe_rasterizer_state *rasterizer,
int num_samples,
enum pipe_format depth_format,
@ -568,27 +563,27 @@ ilo_gpe_gen6_fill_3dstate_sf_raster(const struct ilo_gpe *gpe,
uint32_t *dw, int num_dwords);
void
ilo_gpe_gen6_fill_3dstate_sf_sbe(const struct ilo_gpe *gpe,
ilo_gpe_gen6_fill_3dstate_sf_sbe(const struct ilo_dev_info *dev,
const struct pipe_rasterizer_state *rasterizer,
const struct ilo_shader *fs,
const struct ilo_shader *last_sh,
uint32_t *dw, int num_dwords);
void
ilo_gpe_gen6_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_gpe *gpe,
ilo_gpe_gen6_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_dev_info *dev,
const struct pipe_surface *surface,
const struct pipe_depth_stencil_alpha_state *dsa,
bool hiz,
struct ilo_cp *cp);
void
ilo_gpe_gen6_fill_SF_VIEWPORT(const struct ilo_gpe *gpe,
ilo_gpe_gen6_fill_SF_VIEWPORT(const struct ilo_dev_info *dev,
const struct pipe_viewport_state *viewports,
int num_viewports,
uint32_t *dw, int num_dwords);
void
ilo_gpe_gen6_fill_CLIP_VIEWPORT(const struct ilo_gpe *gpe,
ilo_gpe_gen6_fill_CLIP_VIEWPORT(const struct ilo_dev_info *dev,
const struct pipe_viewport_state *viewports,
int num_viewports,
uint32_t *dw, int num_dwords);

268
src/gallium/drivers/ilo/ilo_gpe_gen7.c
View file

@ -35,21 +35,21 @@
#include "ilo_gpe_gen7.h"
static void
gen7_emit_GPGPU_WALKER(const struct ilo_gpe *gpe,
gen7_emit_GPGPU_WALKER(const struct ilo_dev_info *dev,
struct ilo_cp *cp)
{
assert(!"GPGPU_WALKER unsupported");
}
static void
gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
uint32_t clear_val,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x04);
const uint8_t cmd_len = 3;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | (cmd_len - 2));
@ -59,24 +59,24 @@ gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_dev_info *dev,
const struct pipe_surface *surface,
const struct pipe_depth_stencil_alpha_state *dsa,
bool hiz,
struct ilo_cp *cp)
{
ilo_gpe_gen6_emit_3DSTATE_DEPTH_BUFFER(gpe, surface, dsa, hiz, cp);
ilo_gpe_gen6_emit_3DSTATE_DEPTH_BUFFER(dev, surface, dsa, hiz, cp);
}
static void
gen7_emit_3dstate_pointer(const struct ilo_gpe *gpe,
gen7_emit_3dstate_pointer(const struct ilo_dev_info *dev,
int subop, uint32_t pointer,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
const uint8_t cmd_len = 2;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | (cmd_len - 2));
@ -85,15 +85,15 @@ gen7_emit_3dstate_pointer(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info *dev,
uint32_t color_calc_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x0e, color_calc_state, cp);
gen7_emit_3dstate_pointer(dev, 0x0e, color_calc_state, cp);
}
static void
gen7_emit_3DSTATE_GS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
const struct ilo_shader *gs,
int max_threads, int num_samplers,
struct ilo_cp *cp)
@ -102,7 +102,7 @@ gen7_emit_3DSTATE_GS(const struct ilo_gpe *gpe,
const uint8_t cmd_len = 7;
uint32_t dw2, dw4, dw5;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
if (!gs) {
ilo_cp_begin(cp, cmd_len);
@ -140,7 +140,7 @@ gen7_emit_3DSTATE_GS(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_SF(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
const struct pipe_rasterizer_state *rasterizer,
const struct pipe_surface *zs_surf,
struct ilo_cp *cp)
@ -149,9 +149,9 @@ gen7_emit_3DSTATE_SF(const struct ilo_gpe *gpe,
const uint8_t cmd_len = 7;
uint32_t dw[6];
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
ilo_gpe_gen6_fill_3dstate_sf_raster(gpe, rasterizer,
ilo_gpe_gen6_fill_3dstate_sf_raster(dev, rasterizer,
1, (zs_surf) ? zs_surf->format : PIPE_FORMAT_NONE, true,
dw, Elements(dw));
@ -162,7 +162,7 @@ gen7_emit_3DSTATE_SF(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_WM(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
const struct ilo_shader *fs,
const struct pipe_rasterizer_state *rasterizer,
bool cc_may_kill,
@ -173,7 +173,7 @@ gen7_emit_3DSTATE_WM(const struct ilo_gpe *gpe,
const int num_samples = 1;
uint32_t dw1, dw2;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
dw1 = GEN7_WM_STATISTICS_ENABLE |
GEN7_WM_LINE_AA_WIDTH_2_0;
@ -272,7 +272,7 @@ gen7_emit_3DSTATE_WM(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3dstate_constant(const struct ilo_gpe *gpe,
gen7_emit_3dstate_constant(const struct ilo_dev_info *dev,
int subop,
const uint32_t *bufs, const int *sizes,
int num_bufs,
@ -283,7 +283,7 @@ gen7_emit_3dstate_constant(const struct ilo_gpe *gpe,
uint32_t dw[6];
int total_read_length, i;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
/* VS, HS, DS, GS, and PS variants */
assert(subop >= 0x15 && subop <= 0x1a && subop != 0x18);
@ -340,34 +340,34 @@ gen7_emit_3dstate_constant(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_CONSTANT_VS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info *dev,
const uint32_t *bufs, const int *sizes,
int num_bufs,
struct ilo_cp *cp)
{
gen7_emit_3dstate_constant(gpe, 0x15, bufs, sizes, num_bufs, cp);
gen7_emit_3dstate_constant(dev, 0x15, bufs, sizes, num_bufs, cp);
}
static void
gen7_emit_3DSTATE_CONSTANT_GS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info *dev,
const uint32_t *bufs, const int *sizes,
int num_bufs,
struct ilo_cp *cp)
{
gen7_emit_3dstate_constant(gpe, 0x16, bufs, sizes, num_bufs, cp);
gen7_emit_3dstate_constant(dev, 0x16, bufs, sizes, num_bufs, cp);
}
static void
gen7_emit_3DSTATE_CONSTANT_PS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info *dev,
const uint32_t *bufs, const int *sizes,
int num_bufs,
struct ilo_cp *cp)
{
gen7_emit_3dstate_constant(gpe, 0x17, bufs, sizes, num_bufs, cp);
gen7_emit_3dstate_constant(dev, 0x17, bufs, sizes, num_bufs, cp);
}
static void
gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
unsigned sample_mask,
int num_samples,
struct ilo_cp *cp)
@ -376,7 +376,7 @@ gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_gpe *gpe,
const uint8_t cmd_len = 2;
const unsigned valid_mask = ((1 << num_samples) - 1) | 0x1;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 294:
@ -396,25 +396,25 @@ gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_CONSTANT_HS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_CONSTANT_HS(const struct ilo_dev_info *dev,
const uint32_t *bufs, const int *sizes,
int num_bufs,
struct ilo_cp *cp)
{
gen7_emit_3dstate_constant(gpe, 0x19, bufs, sizes, num_bufs, cp);
gen7_emit_3dstate_constant(dev, 0x19, bufs, sizes, num_bufs, cp);
}
static void
gen7_emit_3DSTATE_CONSTANT_DS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_CONSTANT_DS(const struct ilo_dev_info *dev,
const uint32_t *bufs, const int *sizes,
int num_bufs,
struct ilo_cp *cp)
{
gen7_emit_3dstate_constant(gpe, 0x1a, bufs, sizes, num_bufs, cp);
gen7_emit_3dstate_constant(dev, 0x1a, bufs, sizes, num_bufs, cp);
}
static void
gen7_emit_3DSTATE_HS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_HS(const struct ilo_dev_info *dev,
const struct ilo_shader *hs,
int max_threads, int num_samplers,
struct ilo_cp *cp)
@ -423,7 +423,7 @@ gen7_emit_3DSTATE_HS(const struct ilo_gpe *gpe,
const uint8_t cmd_len = 7;
uint32_t dw1, dw2, dw5;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
if (!hs) {
ilo_cp_begin(cp, cmd_len);
@ -465,13 +465,13 @@ gen7_emit_3DSTATE_HS(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_TE(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_TE(const struct ilo_dev_info *dev,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1c);
const uint8_t cmd_len = 4;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | (cmd_len - 2));
@ -482,7 +482,7 @@ gen7_emit_3DSTATE_TE(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_DS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_DS(const struct ilo_dev_info *dev,
const struct ilo_shader *ds,
int max_threads, int num_samplers,
struct ilo_cp *cp)
@ -491,7 +491,7 @@ gen7_emit_3DSTATE_DS(const struct ilo_gpe *gpe,
const uint8_t cmd_len = 6;
uint32_t dw2, dw4, dw5;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
if (!ds) {
ilo_cp_begin(cp, cmd_len);
@ -531,7 +531,7 @@ gen7_emit_3DSTATE_DS(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_STREAMOUT(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev,
bool enable,
bool rasterizer_discard,
bool flatshade_first,
@ -542,7 +542,7 @@ gen7_emit_3DSTATE_STREAMOUT(const struct ilo_gpe *gpe,
uint32_t dw1, dw2;
int i;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
if (!enable) {
ilo_cp_begin(cp, cmd_len);
@ -573,7 +573,7 @@ gen7_emit_3DSTATE_STREAMOUT(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_SBE(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_SBE(const struct ilo_dev_info *dev,
const struct pipe_rasterizer_state *rasterizer,
const struct ilo_shader *fs,
const struct ilo_shader *last_sh,
@ -583,9 +583,9 @@ gen7_emit_3DSTATE_SBE(const struct ilo_gpe *gpe,
const uint8_t cmd_len = 14;
uint32_t dw[13];
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
ilo_gpe_gen6_fill_3dstate_sf_sbe(gpe, rasterizer,
ilo_gpe_gen6_fill_3dstate_sf_sbe(dev, rasterizer,
fs, last_sh, dw, Elements(dw));
ilo_cp_begin(cp, cmd_len);
@ -595,7 +595,7 @@ gen7_emit_3DSTATE_SBE(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_PS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
const struct ilo_shader *fs,
int max_threads, int num_samplers,
bool dual_blend,
@ -605,7 +605,7 @@ gen7_emit_3DSTATE_PS(const struct ilo_gpe *gpe,
const uint8_t cmd_len = 8;
uint32_t dw2, dw4, dw5;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 286:
@ -673,119 +673,119 @@ gen7_emit_3DSTATE_PS(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(const struct ilo_dev_info *dev,
uint32_t sf_clip_viewport,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x21, sf_clip_viewport, cp);
gen7_emit_3dstate_pointer(dev, 0x21, sf_clip_viewport, cp);
}
static void
gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(const struct ilo_dev_info *dev,
uint32_t cc_viewport,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x23, cc_viewport, cp);
gen7_emit_3dstate_pointer(dev, 0x23, cc_viewport, cp);
}
static void
gen7_emit_3DSTATE_BLEND_STATE_POINTERS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_BLEND_STATE_POINTERS(const struct ilo_dev_info *dev,
uint32_t blend_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x24, blend_state, cp);
gen7_emit_3dstate_pointer(dev, 0x24, blend_state, cp);
}
static void
gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(const struct ilo_dev_info *dev,
uint32_t depth_stencil_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x25, depth_stencil_state, cp);
gen7_emit_3dstate_pointer(dev, 0x25, depth_stencil_state, cp);
}
static void
gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x26, binding_table, cp);
gen7_emit_3dstate_pointer(dev, 0x26, binding_table, cp);
}
static void
gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x27, binding_table, cp);
gen7_emit_3dstate_pointer(dev, 0x27, binding_table, cp);
}
static void
gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x28, binding_table, cp);
gen7_emit_3dstate_pointer(dev, 0x28, binding_table, cp);
}
static void
gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x29, binding_table, cp);
gen7_emit_3dstate_pointer(dev, 0x29, binding_table, cp);
}
static void
gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x2a, binding_table, cp);
gen7_emit_3dstate_pointer(dev, 0x2a, binding_table, cp);
}
static void
gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x2b, sampler_state, cp);
gen7_emit_3dstate_pointer(dev, 0x2b, sampler_state, cp);
}
static void
gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_HS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_HS(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x2c, sampler_state, cp);
gen7_emit_3dstate_pointer(dev, 0x2c, sampler_state, cp);
}
static void
gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_DS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_DS(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x2d, sampler_state, cp);
gen7_emit_3dstate_pointer(dev, 0x2d, sampler_state, cp);
}
static void
gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_GS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_GS(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x2e, sampler_state, cp);
gen7_emit_3dstate_pointer(dev, 0x2e, sampler_state, cp);
}
static void
gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(gpe, 0x2f, sampler_state, cp);
gen7_emit_3dstate_pointer(dev, 0x2f, sampler_state, cp);
}
static void
gen7_emit_3dstate_urb(const struct ilo_gpe *gpe,
gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
int subop, int offset, int size,
int entry_size,
struct ilo_cp *cp)
@ -795,7 +795,7 @@ gen7_emit_3dstate_urb(const struct ilo_gpe *gpe,
const int row_size = 64; /* 512 bits */
int alloc_size, num_entries;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
/* VS, HS, DS, and GS variants */
assert(subop >= 0x30 && subop <= 0x33);
@ -825,9 +825,9 @@ gen7_emit_3dstate_urb(const struct ilo_gpe *gpe,
switch (subop) {
case 0x30: /* 3DSTATE_URB_VS */
assert(num_entries >= 32);
if (gpe->gt == 2 && num_entries > 704)
if (dev->gt == 2 && num_entries > 704)
num_entries = 704;
else if (gpe->gt == 1 && num_entries > 512)
else if (dev->gt == 1 && num_entries > 512)
num_entries = 512;
break;
case 0x32: /* 3DSTATE_URB_DS */
@ -847,39 +847,39 @@ gen7_emit_3dstate_urb(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_URB_VS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_URB_VS(const struct ilo_dev_info *dev,
int offset, int size, int entry_size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_urb(gpe, 0x30, offset, size, entry_size, cp);
gen7_emit_3dstate_urb(dev, 0x30, offset, size, entry_size, cp);
}
static void
gen7_emit_3DSTATE_URB_HS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_URB_HS(const struct ilo_dev_info *dev,
int offset, int size, int entry_size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_urb(gpe, 0x31, offset, size, entry_size, cp);
gen7_emit_3dstate_urb(dev, 0x31, offset, size, entry_size, cp);
}
static void
gen7_emit_3DSTATE_URB_DS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_URB_DS(const struct ilo_dev_info *dev,
int offset, int size, int entry_size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_urb(gpe, 0x32, offset, size, entry_size, cp);
gen7_emit_3dstate_urb(dev, 0x32, offset, size, entry_size, cp);
}
static void
gen7_emit_3DSTATE_URB_GS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_URB_GS(const struct ilo_dev_info *dev,
int offset, int size, int entry_size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_urb(gpe, 0x33, offset, size, entry_size, cp);
gen7_emit_3dstate_urb(dev, 0x33, offset, size, entry_size, cp);
}
static void
gen7_emit_3dstate_push_constant_alloc(const struct ilo_gpe *gpe,
gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info *dev,
int subop, int offset, int size,
struct ilo_cp *cp)
{
@ -887,7 +887,7 @@ gen7_emit_3dstate_push_constant_alloc(const struct ilo_gpe *gpe,
const uint8_t cmd_len = 2;
int end;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
/* VS, HS, DS, GS, and PS variants */
assert(subop >= 0x12 && subop <= 0x16);
@ -938,47 +938,47 @@ gen7_emit_3dstate_push_constant_alloc(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_push_constant_alloc(gpe, 0x12, offset, size, cp);
gen7_emit_3dstate_push_constant_alloc(dev, 0x12, offset, size, cp);
}
static void
gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_HS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_HS(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_push_constant_alloc(gpe, 0x13, offset, size, cp);
gen7_emit_3dstate_push_constant_alloc(dev, 0x13, offset, size, cp);
}
static void
gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_DS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_DS(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_push_constant_alloc(gpe, 0x14, offset, size, cp);
gen7_emit_3dstate_push_constant_alloc(dev, 0x14, offset, size, cp);
}
static void
gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_GS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_GS(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_push_constant_alloc(gpe, 0x15, offset, size, cp);
gen7_emit_3dstate_push_constant_alloc(dev, 0x15, offset, size, cp);
}
static void
gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_push_constant_alloc(gpe, 0x16, offset, size, cp);
gen7_emit_3dstate_push_constant_alloc(dev, 0x16, offset, size, cp);
}
static void
gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x17);
@ -986,7 +986,7 @@ gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_gpe *gpe,
uint16_t decls[128];
int num_decls, i;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
memset(decls, 0, sizeof(decls));
num_decls = 0;
@ -1013,7 +1013,7 @@ gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_gpe *gpe,
gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
int index,
bool enable,
struct ilo_cp *cp)
@ -1022,7 +1022,7 @@ gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_gpe *gpe,
const uint8_t cmd_len = 4;
int start, end;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
if (!enable) {
ilo_cp_begin(cp, cmd_len);
@ -1045,7 +1045,7 @@ gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_gpe *gpe,
}
static void
gen7_emit_3DPRIMITIVE(const struct ilo_gpe *gpe,
gen7_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
const struct pipe_draw_info *info,
bool rectlist,
struct ilo_cp *cp)
@ -1058,7 +1058,7 @@ gen7_emit_3DPRIMITIVE(const struct ilo_gpe *gpe,
GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM :
GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | (cmd_len - 2));
@ -1072,7 +1072,7 @@ gen7_emit_3DPRIMITIVE(const struct ilo_gpe *gpe,
}
static uint32_t
gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_gpe *gpe,
gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_dev_info *dev,
const struct pipe_viewport_state *viewports,
int num_viewports,
struct ilo_cp *cp)
@ -1082,7 +1082,7 @@ gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_gpe *gpe,
uint32_t state_offset, *dw;
int i;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 270:
@ -1102,9 +1102,9 @@ gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_gpe *gpe,
for (i = 0; i < num_viewports; i++) {
const struct pipe_viewport_state *vp = &viewports[i];
ilo_gpe_gen6_fill_SF_VIEWPORT(gpe, vp, 1, dw, 8);
ilo_gpe_gen6_fill_SF_VIEWPORT(dev, vp, 1, dw, 8);
ilo_gpe_gen6_fill_CLIP_VIEWPORT(gpe, vp, 1, dw + 8, 4);
ilo_gpe_gen6_fill_CLIP_VIEWPORT(dev, vp, 1, dw + 8, 4);
dw[12] = 0;
dw[13] = 0;
@ -1118,12 +1118,12 @@ gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_gpe *gpe,
}
static void
gen7_fill_null_SURFACE_STATE(const struct ilo_gpe *gpe,
gen7_fill_null_SURFACE_STATE(const struct ilo_dev_info *dev,
unsigned width, unsigned height,
unsigned depth, unsigned lod,
uint32_t *dw, int num_dwords)
{
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
assert(num_dwords == 8);
/*
@ -1175,7 +1175,7 @@ gen7_fill_null_SURFACE_STATE(const struct ilo_gpe *gpe,
}
static void
gen7_fill_buffer_SURFACE_STATE(const struct ilo_gpe *gpe,
gen7_fill_buffer_SURFACE_STATE(const struct ilo_dev_info *dev,
const struct ilo_resource *res,
unsigned offset, unsigned size,
unsigned struct_size,
@ -1190,7 +1190,7 @@ gen7_fill_buffer_SURFACE_STATE(const struct ilo_gpe *gpe,
int width, height, depth, pitch;
int surface_type, surface_format, num_entries;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
assert(num_dwords == 8);
surface_type = (structured) ? 5 : BRW_SURFACE_BUFFER;
@ -1294,7 +1294,7 @@ gen7_fill_buffer_SURFACE_STATE(const struct ilo_gpe *gpe,
}
static void
gen7_fill_normal_SURFACE_STATE(const struct ilo_gpe *gpe,
gen7_fill_normal_SURFACE_STATE(const struct ilo_dev_info *dev,
struct ilo_resource *res,
enum pipe_format format,
unsigned first_level, unsigned num_levels,
@ -1306,7 +1306,7 @@ gen7_fill_normal_SURFACE_STATE(const struct ilo_gpe *gpe,
int width, height, depth, pitch, lod;
unsigned layer_offset, x_offset, y_offset;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
assert(num_dwords == 8);
surface_type = ilo_gpe_gen6_translate_texture(res->base.target);
@ -1489,7 +1489,7 @@ gen7_fill_normal_SURFACE_STATE(const struct ilo_gpe *gpe,
}
static uint32_t
gen7_emit_SURFACE_STATE(const struct ilo_gpe *gpe,
gen7_emit_SURFACE_STATE(const struct ilo_dev_info *dev,
struct intel_bo *bo, bool for_render,
const uint32_t *dw, int num_dwords,
struct ilo_cp *cp)
@ -1499,7 +1499,7 @@ gen7_emit_SURFACE_STATE(const struct ilo_gpe *gpe,
uint32_t state_offset;
uint32_t read_domains, write_domain;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
assert(num_dwords == state_len);
if (for_render) {
@ -1526,14 +1526,14 @@ gen7_emit_SURFACE_STATE(const struct ilo_gpe *gpe,
}
static uint32_t
gen7_emit_surf_SURFACE_STATE(const struct ilo_gpe *gpe,
gen7_emit_surf_SURFACE_STATE(const struct ilo_dev_info *dev,
const struct pipe_surface *surface,
struct ilo_cp *cp)
{
struct intel_bo *bo;
uint32_t dw[8];
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
if (surface && surface->texture) {
struct ilo_resource *res = ilo_resource(surface->texture);
@ -1544,7 +1544,7 @@ gen7_emit_surf_SURFACE_STATE(const struct ilo_gpe *gpe,
* classic i965 sets render_cache_rw for constant buffers and sol
* surfaces but not render buffers. Why?
*/
gen7_fill_normal_SURFACE_STATE(gpe, res, surface->format,
gen7_fill_normal_SURFACE_STATE(dev, res, surface->format,
surface->u.tex.level, 1,
surface->u.tex.first_layer,
surface->u.tex.last_layer - surface->u.tex.first_layer + 1,
@ -1552,35 +1552,35 @@ gen7_emit_surf_SURFACE_STATE(const struct ilo_gpe *gpe,
}
else {
bo = NULL;
gen7_fill_null_SURFACE_STATE(gpe,
gen7_fill_null_SURFACE_STATE(dev,
surface->width, surface->height, 1, 0, dw, Elements(dw));
}
return gen7_emit_SURFACE_STATE(gpe, bo, true, dw, Elements(dw), cp);
return gen7_emit_SURFACE_STATE(dev, bo, true, dw, Elements(dw), cp);
}
static uint32_t
gen7_emit_view_SURFACE_STATE(const struct ilo_gpe *gpe,
gen7_emit_view_SURFACE_STATE(const struct ilo_dev_info *dev,
const struct pipe_sampler_view *view,
struct ilo_cp *cp)
{
struct ilo_resource *res = ilo_resource(view->texture);
uint32_t dw[8];
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
gen7_fill_normal_SURFACE_STATE(gpe, res, view->format,
gen7_fill_normal_SURFACE_STATE(dev, res, view->format,
view->u.tex.first_level,
view->u.tex.last_level - view->u.tex.first_level + 1,
view->u.tex.first_layer,
view->u.tex.last_layer - view->u.tex.first_layer + 1,
false, false, dw, Elements(dw));
return gen7_emit_SURFACE_STATE(gpe, res->bo, false, dw, Elements(dw), cp);
return gen7_emit_SURFACE_STATE(dev, res->bo, false, dw, Elements(dw), cp);
}
static uint32_t
gen7_emit_cbuf_SURFACE_STATE(const struct ilo_gpe *gpe,
gen7_emit_cbuf_SURFACE_STATE(const struct ilo_dev_info *dev,
const struct pipe_constant_buffer *cbuf,
struct ilo_cp *cp)
{
@ -1588,18 +1588,18 @@ gen7_emit_cbuf_SURFACE_STATE(const struct ilo_gpe *gpe,
struct ilo_resource *res = ilo_resource(cbuf->buffer);
uint32_t dw[8];
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
gen7_fill_buffer_SURFACE_STATE(gpe, res,
gen7_fill_buffer_SURFACE_STATE(dev, res,
cbuf->buffer_offset, cbuf->buffer_size,
util_format_get_blocksize(elem_format), elem_format,
false, false, dw, Elements(dw));
return gen7_emit_SURFACE_STATE(gpe, res->bo, false, dw, Elements(dw), cp);
return gen7_emit_SURFACE_STATE(dev, res->bo, false, dw, Elements(dw), cp);
}
static uint32_t
gen7_emit_SAMPLER_BORDER_COLOR_STATE(const struct ilo_gpe *gpe,
gen7_emit_SAMPLER_BORDER_COLOR_STATE(const struct ilo_dev_info *dev,
const union pipe_color_union *color,
struct ilo_cp *cp)
{
@ -1607,7 +1607,7 @@ gen7_emit_SAMPLER_BORDER_COLOR_STATE(const struct ilo_gpe *gpe,
const int state_len = 4;
uint32_t state_offset, *dw;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
dw = ilo_cp_steal_ptr(cp, "SAMPLER_BORDER_COLOR_STATE",
state_len, state_align, &state_offset);
@ -1617,7 +1617,7 @@ gen7_emit_SAMPLER_BORDER_COLOR_STATE(const struct ilo_gpe *gpe,
}
static int
gen7_estimate_command_size(const struct ilo_gpe *gpe,
gen7_estimate_command_size(const struct ilo_dev_info *dev,
enum ilo_gpe_gen7_command cmd,
int arg)
{
@ -1698,16 +1698,16 @@ gen7_estimate_command_size(const struct ilo_gpe *gpe,
const int body = gen7_command_size_table[cmd].body;
const int count = arg;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
assert(cmd < ILO_GPE_GEN7_COMMAND_COUNT);
return (likely(count)) ? header + body * count : 0;
}
static int
gen7_estimate_state_size(const struct ilo_gpe *gpe,
enum ilo_gpe_gen7_state state,
int arg)
gen7_estimate_state_size(const struct ilo_dev_info *dev,
enum ilo_gpe_gen7_state state,
int arg)
{
static const struct {
int alignment;
@ -1733,7 +1733,7 @@ gen7_estimate_state_size(const struct ilo_gpe *gpe,
const int count = arg;
int estimate;
ILO_GPE_VALID_GEN(gpe, 7, 7);
ILO_GPE_VALID_GEN(dev, 7, 7);
assert(state < ILO_GPE_GEN7_STATE_COUNT);
if (likely(count)) {

86
src/gallium/drivers/ilo/ilo_gpe_gen7.h
View file

@ -137,13 +137,13 @@ typedef ilo_gpe_gen6_MEDIA_INTERFACE_DESCRIPTOR_LOAD ilo_gpe_gen7_MEDIA_INTERFAC
typedef ilo_gpe_gen6_MEDIA_STATE_FLUSH ilo_gpe_gen7_MEDIA_STATE_FLUSH;
typedef void
(*ilo_gpe_gen7_GPGPU_WALKER)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_GPGPU_WALKER)(const struct ilo_dev_info *dev,
struct ilo_cp *cp);
typedef ilo_gpe_gen6_3DSTATE_CLEAR_PARAMS ilo_gpe_gen7_3DSTATE_CLEAR_PARAMS;
typedef void
(*ilo_gpe_gen7_3DSTATE_DEPTH_BUFFER)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_DEPTH_BUFFER)(const struct ilo_dev_info *dev,
const struct pipe_surface *surface,
const struct pipe_depth_stencil_alpha_state *dsa,
bool hiz,
@ -156,7 +156,7 @@ typedef ilo_gpe_gen6_3DSTATE_VERTEX_ELEMENTS ilo_gpe_gen7_3DSTATE_VERTEX_ELEMENT
typedef ilo_gpe_gen6_3DSTATE_INDEX_BUFFER ilo_gpe_gen7_3DSTATE_INDEX_BUFFER;
typedef void
(*ilo_gpe_gen7_3DSTATE_CC_STATE_POINTERS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_CC_STATE_POINTERS)(const struct ilo_dev_info *dev,
uint32_t color_calc_state,
struct ilo_cp *cp);
@ -164,7 +164,7 @@ typedef ilo_gpe_gen6_3DSTATE_SCISSOR_STATE_POINTERS ilo_gpe_gen7_3DSTATE_SCISSOR
typedef ilo_gpe_gen6_3DSTATE_VS ilo_gpe_gen7_3DSTATE_VS;
typedef void
(*ilo_gpe_gen7_3DSTATE_GS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_GS)(const struct ilo_dev_info *dev,
const struct ilo_shader *gs,
int max_threads, int num_samplers,
struct ilo_cp *cp);
@ -172,13 +172,13 @@ typedef void
typedef ilo_gpe_gen6_3DSTATE_CLIP ilo_gpe_gen7_3DSTATE_CLIP;
typedef void
(*ilo_gpe_gen7_3DSTATE_SF)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_SF)(const struct ilo_dev_info *dev,
const struct pipe_rasterizer_state *rasterizer,
const struct pipe_surface *zs_surf,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_WM)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_WM)(const struct ilo_dev_info *dev,
const struct ilo_shader *fs,
const struct pipe_rasterizer_state *rasterizer,
bool cc_may_kill,
@ -189,147 +189,147 @@ typedef ilo_gpe_gen6_3DSTATE_CONSTANT_GS ilo_gpe_gen7_3DSTATE_CONSTANT_GS;
typedef ilo_gpe_gen6_3DSTATE_CONSTANT_PS ilo_gpe_gen7_3DSTATE_CONSTANT_PS;
typedef void
(*ilo_gpe_gen7_3DSTATE_SAMPLE_MASK)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_SAMPLE_MASK)(const struct ilo_dev_info *dev,
unsigned sample_mask,
int num_samples,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_CONSTANT_HS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_CONSTANT_HS)(const struct ilo_dev_info *dev,
const uint32_t *bufs, const int *sizes,
int num_bufs,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_CONSTANT_DS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_CONSTANT_DS)(const struct ilo_dev_info *dev,
const uint32_t *bufs, const int *sizes,
int num_bufs,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_HS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_HS)(const struct ilo_dev_info *dev,
const struct ilo_shader *hs,
int max_threads, int num_samplers,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_TE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_TE)(const struct ilo_dev_info *dev,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_DS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_DS)(const struct ilo_dev_info *dev,
const struct ilo_shader *ds,
int max_threads, int num_samplers,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_STREAMOUT)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_STREAMOUT)(const struct ilo_dev_info *dev,
bool enable,
bool rasterizer_discard,
bool flatshade_first,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_SBE)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_SBE)(const struct ilo_dev_info *dev,
const struct pipe_rasterizer_state *rasterizer,
const struct ilo_shader *fs,
const struct ilo_shader *last_sh,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_PS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_PS)(const struct ilo_dev_info *dev,
const struct ilo_shader *fs,
int max_threads, int num_samplers,
bool dual_blend,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP)(const struct ilo_dev_info *dev,
uint32_t viewport,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC)(const struct ilo_dev_info *dev,
uint32_t viewport,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_BLEND_STATE_POINTERS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_BLEND_STATE_POINTERS)(const struct ilo_dev_info *dev,
uint32_t blend,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS)(const struct ilo_dev_info *dev,
uint32_t depth_stencil,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_VS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_VS)(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_HS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_HS)(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_DS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_DS)(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_GS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_GS)(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_PS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_PS)(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS)(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_HS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_HS)(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_DS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_DS)(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_GS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_GS)(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS)(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_URB_VS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_URB_VS)(const struct ilo_dev_info *dev,
int offset, int size, int entry_size,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_URB_HS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_URB_HS)(const struct ilo_dev_info *dev,
int offset, int size, int entry_size,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_URB_DS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_URB_DS)(const struct ilo_dev_info *dev,
int offset, int size, int entry_size,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_URB_GS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_URB_GS)(const struct ilo_dev_info *dev,
int offset, int size, int entry_size,
struct ilo_cp *cp);
@ -341,36 +341,36 @@ typedef ilo_gpe_gen6_3DSTATE_AA_LINE_PARAMETERS ilo_gpe_gen7_3DSTATE_AA_LINE_PAR
typedef ilo_gpe_gen6_3DSTATE_MULTISAMPLE ilo_gpe_gen7_3DSTATE_MULTISAMPLE;
typedef void
(*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS)(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_HS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_HS)(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_DS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_DS)(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_GS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_GS)(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS)(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_SO_DECL_LIST)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_SO_DECL_LIST)(const struct ilo_dev_info *dev,
struct ilo_cp *cp);
typedef void
(*ilo_gpe_gen7_3DSTATE_SO_BUFFER)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_3DSTATE_SO_BUFFER)(const struct ilo_dev_info *dev,
int index,
bool enable,
struct ilo_cp *cp);
@ -380,7 +380,7 @@ typedef ilo_gpe_gen6_3DPRIMITIVE ilo_gpe_gen7_3DPRIMITIVE;
typedef ilo_gpe_gen6_INTERFACE_DESCRIPTOR_DATA ilo_gpe_gen7_INTERFACE_DESCRIPTOR_DATA;
typedef uint32_t
(*ilo_gpe_gen7_SF_CLIP_VIEWPORT)(const struct ilo_gpe *gpe,
(*ilo_gpe_gen7_SF_CLIP_VIEWPORT)(const struct ilo_dev_info *dev,
const struct pipe_viewport_state *viewports,
int num_viewports,
struct ilo_cp *cp);
@ -404,11 +404,11 @@ typedef ilo_gpe_gen6_push_constant_buffer ilo_gpe_gen7_push_constant_buffer;
* \see ilo_gpe_gen6
*/
struct ilo_gpe_gen7 {
int (*estimate_command_size)(const struct ilo_gpe *gpe,
int (*estimate_command_size)(const struct ilo_dev_info *dev,
enum ilo_gpe_gen7_command cmd,
int arg);
int (*estimate_state_size)(const struct ilo_gpe *gpe,
int (*estimate_state_size)(const struct ilo_dev_info *dev,
enum ilo_gpe_gen7_state state,
int arg);