From 51d5c0d53797cfcc25ac654f4dc643fe21d9aa5e Mon Sep 17 00:00:00 2001 From: David Rosca Date: Mon, 18 Aug 2025 17:10:10 +0200 Subject: [PATCH] radeonsi/vcn: Disable H264/5 constrained intra pred with rate control There is a FW issue when using constrained intra prediction with rate control enabled, causing unexpected quality degradation. Disable it until FW fix is available. Cc: mesa-stable Reviewed-by: Ruijing Dong Part-of: --- src/gallium/drivers/radeonsi/radeon_vcn_enc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c index dc34dc285ca..10720d54b72 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c @@ -292,7 +292,9 @@ static void radeon_vcn_enc_h264_get_spec_misc_param(struct radeon_encoder *enc, enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag = pic->pic_ctrl.redundant_pic_cnt_present_flag; enc->enc_pic.spec_misc.b_picture_enabled = !!pic->seq.max_num_reorder_frames; + /* FW issue when using constrained intra pred with rate control. */ enc->enc_pic.spec_misc.constrained_intra_pred_flag = + !enc->enc_pic.rc_session_init.rate_control_method && pic->pic_ctrl.constrained_intra_pred_flag; enc->enc_pic.spec_misc.half_pel_enabled = 1; enc->enc_pic.spec_misc.quarter_pel_enabled = 1; @@ -628,7 +630,9 @@ static void radeon_vcn_enc_hevc_get_spec_misc_param(struct radeon_encoder *enc, enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag; enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled = pic->seq.strong_intra_smoothing_enabled_flag; + /* FW issue when using constrained intra pred with rate control. */ enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = + !enc->enc_pic.rc_session_init.rate_control_method && pic->pic.constrained_intra_pred_flag; enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag; enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;