From 51bd3b22009469589718936debc7b60e1082df2d Mon Sep 17 00:00:00 2001
From: Christian Gmeiner <cgmeiner@igalia.com>
Date: Fri, 6 Mar 2026 13:34:49 +0100
Subject: [PATCH] etnaviv: isa: Add unary texkill variant

Split texkill_cond into texkill_unary (single source) and texkill_binary
(two sources) variants. Update the compiler to use ISA_OPC_TEXKILL_UNARY for
discard emission since it only uses a single source operand.

Fixes: 081efcd68de ("etnaviv: isa: Split texkill into concrete bitset variants")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40262>
---
 src/etnaviv/isa/etnaviv.xml                   | 50 ++++++++++++++++++-
 .../etnaviv/etnaviv_compiler_nir_emit.c       |  2 +-
 2 files changed, 50 insertions(+), 2 deletions(-)

diff --git a/src/etnaviv/isa/etnaviv.xml b/src/etnaviv/isa/etnaviv.xml
index ff74ff1bdd1..5309611a83c 100644
--- a/src/etnaviv/isa/etnaviv.xml
+++ b/src/etnaviv/isa/etnaviv.xml
@@ -417,6 +417,49 @@ SPDX-License-Identifier: MIT
 	<pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP -->
 </bitset>
 
+<bitset name="#instruction-alu-no-dst-cond-src0" extends="#instruction-alu">
+	<meta type="alu_cond" has_dest="false" valid_srcs="0"/>
+
+	<field name="COND" low="6" high="10" type="#cond"/>
+
+	<display>
+		{INSTR_ALU_COND} {DST:align=18}, {SRC0}, void, void
+	</display>
+
+	<!-- SRC0 -->
+	<pattern pos="43">1</pattern> <!-- SRC0_USE -->
+	<field name="SRC0_REG" low="44" high="52" type="uint"/>
+	<field name="SRC0" low="54" high="63" type="#instruction-src">
+		<param name="SRC0_REG" as="SRC_REG"/>
+		<param name="SRC0_AMODE" as="SRC_AMODE"/>
+		<param name="SRC0_RGROUP" as="SRC_RGROUP"/>
+	</field>
+	<field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/>
+	<field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/>
+
+	<!-- SRC1 -->
+	<pattern pos="70">0</pattern> <!-- SRC1_USE -->
+	<pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG -->
+	<pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ -->
+	<pattern pos="89">0</pattern> <!-- SRC1_NEG -->
+	<pattern pos="90">0</pattern> <!-- SRC1_ABS -->
+	<pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE -->
+	<pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP -->
+
+	<!-- SRC2 -->
+	<pattern pos="99">0</pattern> <!-- SRC2_USE -->
+	<pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG -->
+	<pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ -->
+	<pattern pos="118">0</pattern> <!-- SRC2_NEG -->
+	<pattern pos="119">0</pattern> <!-- SRC2_ABS -->
+	<pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE -->
+	<pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP -->
+
+	<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
+		<map name="COND">src->cond</map>
+	</encode>
+</bitset>
+
 <bitset name="#instruction-alu-no-dst-cond-src0-src1" extends="#instruction-alu">
 	<meta type="alu_cond" has_dest="false" valid_srcs="0|1"/>
 
@@ -1400,7 +1443,12 @@ SPDX-License-Identifier: MIT
 	<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
 </bitset>
 
-<bitset name="texkill_cond" extends="#instruction-alu-no-dst-cond-src0-src1" displayname="texkill">
+<bitset name="texkill_unary" extends="#instruction-alu-no-dst-cond-src0" displayname="texkill">
+	<pattern low="0" high="5">010111</pattern> <!-- OPC -->
+	<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
+</bitset>
+
+<bitset name="texkill_binary" extends="#instruction-alu-no-dst-cond-src0-src1" displayname="texkill">
 	<pattern low="0" high="5">010111</pattern> <!-- OPC -->
 	<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
 </bitset>
diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.c b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.c
index 375aac62486..758052b3601 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.c
@@ -263,7 +263,7 @@ etna_emit_discard(struct etna_compile *c, struct etna_inst_src condition)
    }
 
    struct etna_inst inst = {
-      .opcode = ISA_OPC_TEXKILL,
+      .opcode = ISA_OPC_TEXKILL_UNARY,
       .cond = ISA_COND_NZ,
       .type = (c->info->halti < 2) ? ISA_TYPE_F32 : ISA_TYPE_U32,
       .src[0] = condition,