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iris: remove additional pipe control done before hiz for older gens

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The restriction found in removed comment is not found on new specs.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6593>
This commit is contained in:
Tapani Pälli 2020-09-04 09:56:19 +03:00
parent 320d80f2ce
commit 51a6261d38
1 changed files with 2 additions and 15 deletions
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17
src/gallium/drivers/iris/iris_resolve.c
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@ -551,26 +551,13 @@ iris_hiz_exec(struct iris_context *ice,
* the depth buffer clear operation."
*
* Same applies for Gen8 and Gen9.
*
* In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
* PIPE_CONTROL, Depth Cache Flush Enable:
*
* "This bit must not be set when Depth Stall Enable bit is set in
* this packet."
*
* This is confirmed to hold for real, Haswell gets immediate gpu hangs.
*
* Therefore issue two pipe control flushes, one for cache flush and
* another for depth stall.
*/
iris_emit_pipe_control_flush(batch,
"hiz op: pre-flushes (1/2)",
"hiz op: pre-flush",
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_CS_STALL);
iris_emit_pipe_control_flush(batch, "hiz op: pre-flushes (2/2)",
PIPE_CONTROL_DEPTH_STALL);
assert(isl_aux_usage_has_hiz(res->aux.usage) && res->aux.bo);
iris_batch_maybe_flush(batch, 1500);