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radv,aco: do not lower nir_op_pack_{unorm,snorm}_2x16

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v_cvt_pknorm_{u16,i16}_f32 can be emitted instead, it's supported on
all generations.

No fossils-db changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15215>
This commit is contained in:
Samuel Pitoiset 2022-03-02 15:47:03 +01:00
parent f1f1b3d7f8
commit 516aee64cc
3 changed files with 12 additions and 2 deletions
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10
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -3284,6 +3284,16 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
}
break;
}
case nir_op_pack_unorm_2x16:
case nir_op_pack_snorm_2x16: {
Temp src = get_alu_src(ctx, instr->src[0], 2);
Temp src0 = emit_extract_vector(ctx, src, 0, v1);
Temp src1 = emit_extract_vector(ctx, src, 1, v1);
aco_opcode opcode = instr->op == nir_op_pack_unorm_2x16 ? aco_opcode::v_cvt_pknorm_u16_f32
: aco_opcode::v_cvt_pknorm_i16_f32;
bld.vop3(opcode, Definition(dst), src0, src1);
break;
}
case nir_op_unpack_half_2x16_split_x_flush_to_zero:
case nir_op_unpack_half_2x16_split_x: {
Temp src = get_alu_src(ctx, instr->src[0]);

2
src/amd/compiler/aco_instruction_selection_setup.cpp
View file

@ -515,6 +515,8 @@ init_context(isel_context* ctx, nir_shader* shader)
case nir_op_i2f32:
case nir_op_i2f64:
case nir_op_pack_half_2x16_split:
case nir_op_pack_unorm_2x16:
case nir_op_pack_snorm_2x16:
case nir_op_unpack_half_2x16_split_x:
case nir_op_unpack_half_2x16_split_y:
case nir_op_fddx:

2
src/amd/vulkan/radv_shader.c
View file

@ -66,9 +66,7 @@ get_nir_options_for_stage(struct radv_physical_device *device, gl_shader_stage s
.lower_ineg = true,
.lower_bitfield_insert_to_bitfield_select = true,
.lower_bitfield_extract = true,
.lower_pack_snorm_2x16 = true,
.lower_pack_snorm_4x8 = true,
.lower_pack_unorm_2x16 = true,
.lower_pack_unorm_4x8 = true,
.lower_pack_half_2x16 = true,
.lower_pack_64_2x32 = true,