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dri/radeon: cleanup the radeon_context vtbl

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Remove the set-but-unused, and set-but-empty vtable entries.
Most likely a leftover from the dri1 days.

Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Emil Velikov 2014-08-20 19:51:30 +01:00
parent dd46f0926d
commit 515ffb6c93
8 changed files with 0 additions and 163 deletions
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24
src/mesa/drivers/dri/r200/r200_context.c
View file

@ -143,27 +143,6 @@ static void r200InitDriverFuncs( struct dd_function_table *functions )
}
static void r200_get_lock(radeonContextPtr radeon)
{
r200ContextPtr rmesa = (r200ContextPtr)radeon;
drm_radeon_sarea_t *sarea = radeon->sarea;
R200_STATECHANGE( rmesa, ctx );
if (rmesa->radeon.sarea->tiling_enabled) {
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
}
else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~R200_COLOR_TILE_ENABLE;
if ( sarea->ctx_owner != rmesa->radeon.dri.hwContext ) {
sarea->ctx_owner = rmesa->radeon.dri.hwContext;
}
}
static void r200_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
{
}
static void r200_emit_query_finish(radeonContextPtr radeon)
{
BATCH_LOCALS(radeon);
@ -180,9 +159,6 @@ static void r200_emit_query_finish(radeonContextPtr radeon)
static void r200_init_vtbl(radeonContextPtr radeon)
{
radeon->vtbl.get_lock = r200_get_lock;
radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset;
radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header;
radeon->vtbl.swtcl_flush = r200_swtcl_flush;
radeon->vtbl.fallback = r200Fallback;
radeon->vtbl.update_scissor = r200_vtbl_update_scissor;

52
src/mesa/drivers/dri/r200/r200_state.c
View file

@ -1616,58 +1616,6 @@ static void r200DepthRange(struct gl_context *ctx)
r200UpdateWindow( ctx );
}
void r200UpdateViewportOffset( struct gl_context *ctx )
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
__DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
GLfloat xoffset = (GLfloat)0;
GLfloat yoffset = (GLfloat)dPriv->h;
const GLfloat *v = ctx->ViewportArray[0]._WindowMap.m;
float_ui32_type tx;
float_ui32_type ty;
tx.f = v[MAT_TX] + xoffset;
ty.f = (- v[MAT_TY]) + yoffset;
if ( rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] != tx.ui32 ||
rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] != ty.ui32 )
{
/* Note: this should also modify whatever data the context reset
* code uses...
*/
R200_STATECHANGE( rmesa, vpt );
rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = tx.ui32;
rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = ty.ui32;
/* update polygon stipple x/y screen offset */
{
GLuint stx, sty;
GLuint m = rmesa->hw.msc.cmd[MSC_RE_MISC];
m &= ~(R200_STIPPLE_X_OFFSET_MASK |
R200_STIPPLE_Y_OFFSET_MASK);
/* add magic offsets, then invert */
stx = 31 - ((-1) & R200_STIPPLE_COORD_MASK);
sty = 31 - ((dPriv->h - 1)
& R200_STIPPLE_COORD_MASK);
m |= ((stx << R200_STIPPLE_X_OFFSET_SHIFT) |
(sty << R200_STIPPLE_Y_OFFSET_SHIFT));
if ( rmesa->hw.msc.cmd[MSC_RE_MISC] != m ) {
R200_STATECHANGE( rmesa, msc );
rmesa->hw.msc.cmd[MSC_RE_MISC] = m;
}
}
}
radeonUpdateScissor( ctx );
}
/* =============================================================
* Miscellaneous
*/

1
src/mesa/drivers/dri/r200/r200_state.h
View file

@ -43,7 +43,6 @@ extern void r200InitTnlFuncs( struct gl_context *ctx );
extern void r200UpdateMaterial( struct gl_context *ctx );
extern void r200UpdateViewportOffset( struct gl_context *ctx );
extern void r200UpdateWindow( struct gl_context *ctx );
extern void r200UpdateDrawBuffer(struct gl_context *ctx);

3
src/mesa/drivers/dri/radeon/radeon_common.c
View file

@ -515,9 +515,6 @@ static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean emitAll)
{
struct radeon_state_atom *atom;
if (radeon->vtbl.pre_emit_atoms)
radeon->vtbl.pre_emit_atoms(radeon);
/* Emit actual atoms */
if (radeon->hw.all_dirty || emitAll) {
foreach(atom, &radeon->hw.atomlist)

4
src/mesa/drivers/dri/radeon/radeon_common_context.h
View file

@ -464,11 +464,7 @@ struct radeon_context {
} query;
struct {
void (*get_lock)(radeonContextPtr radeon);
void (*update_viewport_offset)(struct gl_context *ctx);
void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
void (*swtcl_flush)(struct gl_context *ctx, uint32_t offset);
void (*pre_emit_atoms)(radeonContextPtr rmesa);
void (*pre_emit_state)(radeonContextPtr rmesa);
void (*fallback)(struct gl_context *ctx, GLuint bit, GLboolean mode);
void (*free_context)(struct gl_context *ctx);

26
src/mesa/drivers/dri/radeon/radeon_context.c
View file

@ -92,29 +92,6 @@ static const struct tnl_pipeline_stage *radeon_pipeline[] = {
NULL,
};
static void r100_get_lock(radeonContextPtr radeon)
{
r100ContextPtr rmesa = (r100ContextPtr)radeon;
drm_radeon_sarea_t *sarea = radeon->sarea;
RADEON_STATECHANGE(rmesa, ctx);
if (rmesa->radeon.sarea->tiling_enabled) {
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
RADEON_COLOR_TILE_ENABLE;
} else {
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
~RADEON_COLOR_TILE_ENABLE;
}
if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
sarea->ctx_owner = rmesa->radeon.dri.hwContext;
}
}
static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
{
}
static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
{
r100ContextPtr rmesa = (r100ContextPtr)radeon;
@ -146,9 +123,6 @@ static void r100_emit_query_finish(radeonContextPtr radeon)
static void r100_init_vtbl(radeonContextPtr radeon)
{
radeon->vtbl.get_lock = r100_get_lock;
radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
radeon->vtbl.swtcl_flush = r100_swtcl_flush;
radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
radeon->vtbl.fallback = radeonFallback;

52
src/mesa/drivers/dri/radeon/radeon_state.c
View file

@ -1399,58 +1399,6 @@ static void radeonDepthRange(struct gl_context *ctx)
radeonUpdateWindow( ctx );
}
void radeonUpdateViewportOffset( struct gl_context *ctx )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
__DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
GLfloat xoffset = 0.0;
GLfloat yoffset = (GLfloat)dPriv->h;
const GLfloat *v = ctx->ViewportArray[0]._WindowMap.m;
float_ui32_type tx;
float_ui32_type ty;
tx.f = v[MAT_TX] + xoffset + SUBPIXEL_X;
ty.f = (- v[MAT_TY]) + yoffset + SUBPIXEL_Y;
if ( rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] != tx.ui32 ||
rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] != ty.ui32 )
{
/* Note: this should also modify whatever data the context reset
* code uses...
*/
RADEON_STATECHANGE( rmesa, vpt );
rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = tx.ui32;
rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = ty.ui32;
/* update polygon stipple x/y screen offset */
{
GLuint stx, sty;
GLuint m = rmesa->hw.msc.cmd[MSC_RE_MISC];
m &= ~(RADEON_STIPPLE_X_OFFSET_MASK |
RADEON_STIPPLE_Y_OFFSET_MASK);
/* add magic offsets, then invert */
stx = 31 - ((-1) & RADEON_STIPPLE_COORD_MASK);
sty = 31 - ((dPriv->h - 1)
& RADEON_STIPPLE_COORD_MASK);
m |= ((stx << RADEON_STIPPLE_X_OFFSET_SHIFT) |
(sty << RADEON_STIPPLE_Y_OFFSET_SHIFT));
if ( rmesa->hw.msc.cmd[MSC_RE_MISC] != m ) {
RADEON_STATECHANGE( rmesa, msc );
rmesa->hw.msc.cmd[MSC_RE_MISC] = m;
}
}
}
radeonUpdateScissor( ctx );
}
/* =============================================================
* Miscellaneous
*/

1
src/mesa/drivers/dri/radeon/radeon_state.h
View file

@ -44,7 +44,6 @@ extern void radeonInitStateFuncs( struct gl_context *ctx );
extern void radeonUpdateMaterial( struct gl_context *ctx );
extern void radeonUpdateViewportOffset( struct gl_context *ctx );
extern void radeonUpdateWindow( struct gl_context *ctx );
extern void radeonUpdateDrawBuffer( struct gl_context *ctx );
extern void radeonUploadTexMatrix( r100ContextPtr rmesa,