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intel/hwconfig: Sync hwconfig with IGT

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intel-gpu-tools have a few more entries in enum intel_hwconfig, so
adding the missing ones to Mesa.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34157>
This commit is contained in:
José Roberto de Souza 2024-12-03 09:47:55 -08:00 • committed by Marge Bot
parent e3741a5731
commit 512b433172
2 changed files with 28 additions and 3 deletions
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10
src/intel/dev/intel_hwconfig.c
View file

@ -117,6 +117,16 @@ key_to_name(uint32_t key)
HANDLE(INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE);
HANDLE(INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB);
HANDLE(INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB);
HANDLE(INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE);
HANDLE(INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK);
HANDLE(INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES);
HANDLE(INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES);
HANDLE(INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES);
HANDLE(INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES);
HANDLE(INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES);
HANDLE(INTEL_HWCONFIG_MAX_GSC);
HANDLE(INTEL_HWCONFIG_SYNC_NUM_RT_STACKS_PER_DSS);
HANDLE(INTEL_HWCONFIG_NUM_XECU);
#undef HANDLE
}
return "UNKNOWN_INTEL_HWCONFIG";

21
src/intel/dev/intel_hwconfig_types.h
View file

@ -87,18 +87,33 @@ enum intel_hwconfig {
INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE, /* 74 */
INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK, /* 75 */
INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES, /* 76 */
INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES, /* 77 */
INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES, /* 78 */
INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES, /* 79 */
INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES, /* 80 */
INTEL_HWCONFIG_MAX_GSC, /* 81 */
INTEL_HWCONFIG_SYNC_NUM_RT_STACKS_PER_DSS, /* 82 */
INTEL_HWCONFIG_NUM_XECU, /* 83 */
__INTEL_HWCONFIG_LIMIT
};
enum {
INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
INTEL_HWCONFIG_MEMORY_TYPE_HBM2,
INTEL_HWCONFIG_MEMORY_TYPE_HBM2e,
INTEL_HWCONFIG_MEMORY_TYPE_GDDR6,
__INTEL_HWCONFIG_MEMORY_TYPE_LIMIT
};
enum {
INTEL_HWCONFIG_CACHE_TYPE_L3 = 1 << 0,
INTEL_HWCONFIG_CACHE_TYPE_LLC = 1 << 1,
INTEL_HWCONFIG_CACHE_TYPE_EDRAM = 1 << 2,
INTEL_HWCONFIG_CACHE_TYPE_L3 = 0,
INTEL_HWCONFIG_CACHE_TYPE_LLC,
INTEL_HWCONFIG_CACHE_TYPE_EDRAM,
__INTEL_HWCONFIG_CACHE_TYPE_LIMIT
};
#endif /* _INTEL_HWCONFIG_TYPES_H_ */